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programmable touch controller for single electrode capacitance sensors AD7148 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 analog devices, inc. all rights reserved. features programmable capacitance-to-digital converter (cdc) femtofarad (ff) resolution 8 capacitance sensor inputs 25 ms update rate, all 8 sensor inputs no external rc components required automatic conversion sequencer on-chip automatic calibration logic automatic compensation for environmental changes automatic adaptive threshold and sensitivity levels register map compatible with ad7143 on-chip ram to store calibration data i 2 c-compatible serial interface separate v drive level for serial interface interrupt output 16-lead, 4 mm 4 mm lfcsp 2.6 v to 3.3 v supply voltage low operating current full power mode: 1 ma low power mode: 21.5 a applications cell phones personal music and multimedia players smart handheld devices television, a/v, and remote controls gaming consoles digital still cameras general description the AD7148 is designed for use with capacitance sensors imple- menting functions such as buttons, scroll bars, and wheels. the sensors need only one pcb layer, enabling ultrathin applications. the AD7148 is an integrated capacitance-to-digital converter (cdc) with on-chip environmental calibration. the cdc has eight inputs channeled through a switch matrix to a 16-bit, 250 khz sigma-delta (-) converter. the cdc is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation. the external sensors can be arranged as a series of buttons, as a scroll bar or wheel, or as a combination of sensor types. by programming the registers, the user has full control over the cdc setup. high resolution sensors require minimal software to run on the host processor. functional block diagram 0 7155-001 gnd v cc v drive sda sclk switch matrix serial interface and control logic interrupt and gpio logic power-on reset logic calibration ram control and data registers calibration engine bias 6 7 8 a c shield 5 cin0 13 cin1 14 cin2 15 cin3 16 cin4 1 cin5 2 cin6 3 cin7 4 9 10 11 12 int AD7148 16-bit - cdc excitation source figure 1. the AD7148 is designed for single electrode capacitance sensors (grounded sensors). there is an active shield output to minimize noise pickup in the sensor. for floating, or two, electrode sensors, use the ad7143. the AD7148 has on-chip calibration logic to compensate for changes in the ambient environment. the calibration sequence is performed automatically and at continuous intervals as long as the sensors are not touched. this ensures that there are no false or nonregistering touches on the external sensors due to a changing environment. the AD7148 has an i 2 c?-compatible serial interface, as well as an interrupt output. there is a v drive pin to set the voltage level for the serial interface independent of v cc . the AD7148 is available in a 16-lead, 4 mm 4 mm lfcsp and operates from a 2.6 v to 3.6 v supply. the operating current consumption in low power mode is typically 26 a.
AD7148 rev. 0 | page 2 of 56 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 typical average current in low power mode ......................... 4 maximum average current in low power mode.................... 4 i 2 c timing specifications (AD7148-1) ..................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 10 capacitance sensing theory..................................................... 10 bias pin....................................................................................... 11 operating modes........................................................................ 11 capacitance-to-digital converter................................................ 13 oversampling the cdc output ............................................... 13 capacitance sensor offset control.......................................... 13 conversion sequencer ............................................................... 13 cdc conversion sequence time ............................................ 14 cdc conversion results........................................................... 15 capacitance sensor input configuration.................................... 16 cinx input multiplexer setup .................................................. 16 single-ended connections to the cdc .................................. 16 noncontact proximity detection ................................................. 17 recalibration ............................................................................... 18 proximity sensitivity.................................................................. 20 ff_skip_cnt............................................................................ 20 environmental calibration ........................................................... 22 capacitance sensor behavior without calibration............... 22 capacitance sensor behavior with calibration...................... 22 slow fifo ................................................................................ 23 slow_filter_update_lvl .............................................. 23 adaptive threshold and sensitivity ............................................. 24 interrupt output............................................................................. 26 cdc conversion-complete interrupt .................................... 26 sensor touch interrupt.............................................................. 26 ac shield output .............................................................................. 27 i 2 c-compatible serial interface ................................................... 28 v drive input ................................................................................. 30 pcb design guidelines ................................................................. 31 capacitive sensor board mechanical specifications ............. 31 chip scale packages ................................................................... 31 power-up sequence ....................................................................... 32 typical application circuit ........................................................... 33 register map ................................................................................... 34 detailed register descriptions ..................................................... 35 bank 1 registers ......................................................................... 35 bank 2 registers ......................................................................... 43 bank 3 registers ......................................................................... 48 outline dimensions ....................................................................... 56 ordering guide .......................................................................... 56 revision history 12/07revision 0: initial version
AD7148 rev. 0 | page 3 of 56 specifications v cc = 2.6 v to 3.6 v, t a = ?40 o c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments capacitance-to-digital converter update rate 24.25 25 25.75 ms 8 conversion stages in sequencer; decimation rate = 256 resolution 16 bits cinx input range 8 pf no missing codes 16 bits guaranteed by design, not production tested total unadjusted error 20 % output noise (peak-to-peak) 7 codes decimation rate = 128 3 codes decimation rate = 256 output noise (rms) 0.8 codes decimation rate = 128 0.5 codes decimation rate = 256 c stray offset range 20 pf 6-bit dac c stray offset resolution 0.32 pf low power mode delay accuracy 4 % % of 200 ms, 400 ms, 600 ms, or 800 ms excitation source frequency 250 khz output voltage 0 v cc v oscillating ac shield short-circuit source current 10 ma short-circuit sink current 10 ma maximum output load 150 pf capacitance load on ac shield to ground logic inputs (sclk, sda,) input high voltage, v ih 0.7 v drive v input low voltage, v il 0.4 v input high voltage, i ih ?1 a v in = v drive input low voltage, i il 1 a v in = gnd hysteresis 150 mv open-drain outputs (sclk, sda, int ) output low voltage, v ol 0.4 v i sink = ?1 ma output high leakage current, i oh +0.1 1 a v out = v drive power v cc 2.6 3.3 3.6 v v drive 1.65 3.6 v serial interface operating voltage i cc 0.9 1 ma in full power mode, v cc + v drive 15.5 21.5 a low power mode, converter idle, v cc + v drive 2.3 7.5 a full shutdown, v cc + v drive
AD7148 rev. 0 | page 4 of 56 typical average current in low power mode v cc = 3.6 v, t = 25c, load of 50 pf, unless otherwise noted. table 2. current values of conversion stages (a) low power mode delay decimation rate 1 2 3 4 5 6 7 8 200 ms 64 20.83 24.18 27.52 30.82 34.11 37.37 40.6 43.81 128 25.3 31.92 38.45 44.87 51.21 57.45 63.6 69.66 256 34.11 46.99 59.51 71.66 83.47 94.94 106.1 116.96 400 ms 64 18.17 19.86 21.55 23.23 24.9 26.57 28.23 29.88 128 20.43 23.79 27.12 30.43 33.72 36.98 40.22 43.43 256 24.9 31.53 38.06 44.5 50.83 57.08 63.23 69.3 600 ms 64 17.28 18.41 19.54 20.67 21.79 22.91 24.03 25.14 128 18.79 21.04 23.28 25.51 27.73 29.94 32.13 34.32 256 21.79 26.25 30.67 35.04 39.37 43.66 47.9 52.11 800 ms 64 16.84 17.69 18.53 19.38 20.23 21.07 21.91 22.75 128 17.97 19.66 21.35 23.03 24.7 26.37 28.03 29.69 256 20.23 23.59 26.93 30.24 33.53 36.79 40.03 43.24 maximum average current in low power mode v cc = 3.6 v, load of 50 pf, unless otherwise noted. table 3. current values of conversion stages (a) low power mode delay decimation rate 1 2 3 4 5 6 7 8 200 ms 64 27.71 31.65 35.56 39.44 43.28 47.1 50.89 54.64 128 32.96 40.72 48.37 55.89 63.3 70.59 77.77 84.84 256 43.28 58.37 72.99 87.17 100.92 114.26 127.22 139.8 400 ms 64 24.61 26.6 28.58 30.55 32.51 34.47 36.42 38.36 128 27.26 31.21 35.12 39 42.85 46.67 50.46 54.22 256 32.51 40.29 47.94 55.47 62.88 70.18 77.36 84.44 600 ms 64 23.58 24.91 26.23 27.55 28.87 30.18 31.5 32.8 128 25.35 27.99 30.62 33.24 35.84 38.43 41 43.56 256 28.87 34.11 39.29 44.41 49.48 54.5 59.46 64.38 800 ms 64 23.06 24.06 25.05 26.05 27.04 28.03 29.02 30 128 24.39 26.38 28.36 30.33 32.29 34.25 36.2 38.14 256 27.04 30.98 34.9 38.78 42.64 46.46 50.25 54.01
AD7148 rev. 0 | page 5 of 56 i 2 c timing specifications (AD7148-1) t a = ?40c to +85c, v drive = 1.65 v to 3.6 v, v cc = 2.6 v to 3.6 v, unless otherwise noted. sample tested at 25c to ensure compliance. all input signals timed from a voltage level of 1.6 v. table 4. parameter 1 limit unit description f sclk 400 khz max t 1 0.6 s min start condition hold time, t hd; sta t 2 1.3 s min clock low period, t low t 3 0.6 s min clock high period, t high t 4 100 ns min data setup time, t su; dat t 5 300 ns min data hold time, t hd; dat t 6 0.6 s min stop condition setup time, t su; sto t 7 0.6 s min start condition setup time, t su; sta t 8 1.3 s min bus free time between stop and start conditions, t buf t r 300 ns max clock/data rise time t f 300 ns max clock/data fall time 1 guaranteed by design, not production tested. i 2 c timing diagram 07155-002 sclk sda t r t f t 2 t 5 t 1 t 3 t 4 stop start stop start t 7 t 6 t 1 t 8 figure 2. i 2 c detailed timing diagram
AD7148 rev. 0 | page 6 of 56 absolute maximum ratings table 5. parameter rating v cc to gnd ?0.3 v to +3.6 v analog input voltage to gnd ?0.3 v to v cc + 0.3 v digital input voltage to gnd ?0.3 v to v drive + 0.3 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v input current to any pin except supplies 1 10 ma esd rating (human body model) 2.5 kv operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c lfcsp power dissipation 450 mw ja thermal impedance 135.7c/w ir reflow peak temperature 260c 0.5c lead temperature (soldering, 10 sec) 300c 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 200a i ol 200a i oh 1.6v to output pin c l 50pf 07155-003 figure 3. load circuit for digita l output timing specifications esd caution
AD7148 rev. 0 | page 7 of 56 pin configuration and fu nction descriptions 07155-004 pin 1 indicator 1 c in4 2 c in5 3 c in6 4 c in7 11 sclk 12 int 10 sda 9v drive 5 a c s h i e l d 6 b i a s 7 g n d 8 v c c 1 5 c i n 2 1 6 c i n 3 1 4 c i n 1 1 3 c i n 0 AD7148 top view (not to scale) figure 4. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 cin4 capacitance sensor input. 2 cin5 capacitance sensor input. 3 cin6 capacitance sensor input. 4 cin7 capacitance sensor input. 5 ac shield cdc active shield output. connect to external shield. 6 bias bias node for internal circuitry. requires 10 nf capacitor to ground. 7 gnd ground reference point for all circuitry. 8 v cc supply voltage. 9 v drive serial interface operating voltage supply. 10 sda i 2 c serial data input/output. sd a requires pull-up resistor. 11 sclk clock input for serial interface. 12 int general-purpose open-drain interrupt output. programmable polarity; requires pull-up resistor. 13 cin0 capacitance sensor input. 14 cin1 capacitance sensor input. 15 cin2 capacitance sensor input. 16 cin3 capacitance sensor input.
AD7148 rev. 0 | page 8 of 56 typical performance characteristics 935 795 2.6 3.7 07155-005 v cc (v) i cc (a) 915 895 875 855 835 815 2.72.82.93.03.13.23.33.43.53.6 decimation = 256 decimation = 128 decimation = 64 figure 5. supply current vs. supply voltage 180 0 2.5 3.7 07155-006 v cc (v) i cc ( a) 160 140 120 100 80 60 40 20 200ms 400ms 600ms 800ms 2.72.93.13.33.5 figure 6. low power supply current vs. supply voltage, decimation rate = 256 0.12 0 2.5 3.7 07155-007 v cc (v) i cc ( m a) 0.10 0.08 0.06 0.04 0.02 400ms 800ms 600ms 200ms 2.7 2.9 3.1 3.3 3.5 figure 7. low power supply current vs. supply voltage decimation rate = 128 2.5 0 2.7 07155-008 v cc (v) i cc (a) 2.0 1.5 1.0 0.5 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 figure 8. shutdown supply current vs. supply voltage 70 0 07155-009 v cc (v) i cc ( a) 60 50 40 30 20 10 600ms 800ms 200ms 400ms 2.5 3.7 2.72.93.13.33.5 figure 9. low power supply current vs. supply voltage, decimation rate = 64 1150 900 0 07155-010 ac shield capacitive load (pf) i cc (a) 1100 1050 1000 950 100 200 300 400 500 figure 10. supply current vs. capacitive load on cin
AD7148 rev. 0 | page 9 of 56 58000 40000 0 07155-046 ac shield capacitive load (pf) cdc code (d) 100 200 300 400 500 56000 54000 52000 50000 48000 46000 44000 42000 figure 11. cdc output code vs. capacitive load on ac shield 960 780 ?60 ?40 ?20 0 20 40 60 80 100 120 07155-011 temperature (c) i cc (a) 940 920 900 880 860 840 820 800 3.3v 3.6v 2.6v figure 12. supply current vs. temperature 12 0 ?45 135 07155-012 temperature (c) i cc ( a) 10 8 6 4 2 ?25?51535557595115 3.6v 2.6v 3.3v figure 13. shutdown suppl y current vs. temperature 160 0 25 50 100 200 400 800 1600 3200 6400 12800 25600 51200 102400 204800 409600 819200 1640000 07155-013 sine wave frequency (hz) cdc noise p-p (lsb) 140 120 100 80 60 40 20 25mv 75mv 125mv 175mv 50mv 100mv 150mv 200mv figure 14. power supply sine wave rejection, v cc = 3.6 v 35 0 0 10000 20000 30000 40000 50000 60000 07155-014 cdc output code input cap a cit a nce (pf) 30 25 20 15 10 5 figure 15. cdc linearity, v cc = 3.3 v
AD7148 rev. 0 | page 10 of 56 theory of operation the AD7148 is a capacitance-to-digital converter (cdc) with on-chip environmental compensation, intended for use in portable systems requiring high resolution user input. the internal circuitry consists of a 16-bit, - converter that converts a capacitive input signal into a digital value. there are eight input pins on the AD7148: cin0 to cin7. a switch matrix routes the input signals to the cdc. the result of each capacitance-to-digital conversion is stored in on-chip registers. the host subsequently reads the results over the serial interface. the AD7148 has an i 2 c interface, ensuring that the part is compatible with a wide range of host processors. the AD7148 interfaces with up to eight external capacitance sensors. these sensors can be arranged as buttons, scroll bars, wheels, or as a combination of sensor types. the external sensors consist of an electrode on a single or multiple layer pcb that interfaces directly to the AD7148. the AD7148 can be set up to implement any set of input sensors by programming the on-chip registers. the registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. there is an on-chip sequencer to control how each of the capacitance inputs is polled. the AD7148 has on-chip digital logic and 528 words of ram that are used for environmental compensation. the effects of humidity, temperature, and other environmental factors can affect the operation of capacitance sensors. transparent to the user, the AD7148 performs continuous calibration to compen- sate for these effects, allowing the AD7148 to give error-free results at all times. the AD7148 requires minimal companion software that runs on the host or other microcontroller to implement high resolution sensor functions, such as scroll bars or wheels. however, no companion software is required to implement buttons. button sensors are implemented on chip, entirely in digital logic. the AD7148 can be programmed to operate in either full power mode or low power, automatic wake-up mode. the automatic wake-up mode is particularly suited for portable devices that require low power operation, providing the user with significant power savings and full functionality. the AD7148 has an interrupt output, int , to indicate when new data has been placed into the registers. int is used to interrupt the host on sensor activation. the AD7148 operates from a 2.6 v to 3.6 v supply and is available in a 16-lead, 4 mm 4 mm lfcsp. capacitance sensing theory the AD7148 measures capacitance changes from sensors where one plate is connected to ground. the sensor electrode on the pcb makes up one plate of a virtual capacitor. the other plate of the capacitor is the users finger, which is grounded with respect to the sensor input. the AD7148 first outputs an excitation signal to charge the plate of the capacitor. when the user comes close to the sensor, the virtual capacitor is formed, with the user acting as the second capacitor plate. 07155-0015 - adc plastic cover AD7148 sensor pcb excitation signal 250khz mux 16-bit data figure 16. capacitance sensing method a square wave excitation signal is applied to the cinx input during the conversion, and the modulator continuously samples the charge going through the cinx pin. the output of the modulator is processed via a digital filter, and the resulting digital data is stored in the cdc_result_sx registers for each conversion stage, located at address 0x00b to address 0x012.
AD7148 rev. 0 | page 11 of 56 registering a sensor activation when a user approaches a sensor, the total capacitance associated with that sensor changes and is measured by the AD7148. when the capacitance changes to such an extent that a set threshold is exceeded, the AD7148 registers this as a sensor activation. on-chip threshold limits are used to determine when sensor acti- vation occurs. figure 17 shows the change in cdc_result_sx that occurs when a user activates a sensor. the sensor is deemed to be active only when the value of cdc_result_sx is either greater than the value of stagex_high_threshold or less than the value of stagex_low_threshold. cdc output codes stagex_high_threshold stagex_low_threshold ambient or no-touch value sensor active (a) cdc_result_sx 07155-016 sensor active (b) figure 17. sensor activation thresholds in figure 17 , two different sensor activations are shown. sensor activate (a) occurs when a sensor is connected to the positive input of the converter. in this case, when a user activates the sensor, there is an increase in the cdc code, and the value of cdc_result_sx exceeds the value of stagex_high_ threshold. sensor active (b) occurs when the sensor is connected to the negative input of the converter. in this case, when a user activates the sensor, there is a decrease in the cdc code, and the value of cdc_result_sx becomes less than the value of stagex_low_threshold. for each conversion stage, the stagex_high_threshold and the stagex_low_threshold registers are in register bank 3. the values in these registers are updated automatically by the AD7148 due to its environmental calibration and adaptive threshold logic. at power-up, the values in the stagex_high_threshold and stagex_low_threshold registers are the same as those in the stagex_offset_high and stagex_offset_low registers in register bank 2. the user must program the stagex_ offset_high and stagex_offset_low registers on device power-up. see the environmental calibration section for more information. complete solution for capacitance sensing analog devices, inc., provides a complete solution for capacitance sensing. the two main elements of the solution are the sensor pcb and the AD7148. if the application requires high resolution sensors such as scroll bars or wheels, software is required that runs on the host processor. no position algorithm is required for button sensors. the memory requirements for the host depend on the sensor and are typically 10 kb of code and 600 bytes of data memory, depending on the sensor type. 07155-017 AD7148 spi or i 2 c sensor pcb host processor 1 mips 10kb rom 600 bytes ram figure 18. three-part capacitance sensing solution analog devices supplies the sensor pcb footprint design libraries to the customer and supplies any necessary software on an open- source basis. bias pin the bias pin (pin 6) is connected internally to the bias node in the AD7148. to ensure correct operation of the AD7148, connect a 10 nf capacitor between the bias pin and ground. the voltage at the bias pin is v cc /2. operating modes the AD7148 has three operating modes. full power mode, in which the device is always fully po wered, is suited for applications where power is not a concern (for example, game consoles that have an ac power supply). low power mode, in which the part automatically powers down, is tailored to give significant power savings over full power mode and is suited for mobile applications where power must be conserved. in shutdown mode, the part shuts down completely. the power_mode bits of the pwr_control register (address 0x000[1:0]) set the operating mode on the AD7148. table 7 shows the power_mode settings for each operating mode. to put the AD7148 into shutdown mode, set the power_mode bits to either 01 or 11. table 7. power_mode settings power_mode bits operating mode 00 full power mode 01 shutdown mode 10 low power mode 11 shutdown mode the power-on default setting of the power_mode bits is 00, full power mode. full power mode in full power mode, all sections of the AD7148 remain fully powered and converting at all times. while a sensor is being touched, the AD7148 processes the sensor data. if no sensor is touched, the AD7148 measures the ambient capacitance level and uses this data for the on-chip compensation routines. in full power mode, the AD7148 converts at a constant rate. see the cdc conversion sequence time section for more information.
AD7148 rev. 0 | page 12 of 56 low power mode when in low power mode, the power_mode bits are set to 10 upon device initialization. if the external sensors are not touched, the AD7148 reduces its conversion frequency, thereby greatly reducing its power consumption. the part remains in a reduced power state while the sensors are not touched. after a delay defined by the lp_conv_delay bits (200 ms, 400 ms, 600 ms or 800 ms), the ad 7148 performs a conversion and uses this data to update the compensation logic. when an external sensor is touched, the AD7148 begins a conver- sion sequence every 25 ms to read back data from the sensors. in low power mode, total current consumption is an average of the current used during a conversion and the current used while the AD7148 is waiting for the next conversion to begin. for example, when lp_conv_delay is 400 ms, the AD7148 typically uses 0.85 ma current for 25 ms and 14 a for 400 ms during the conversion interval. note that these conversion timings can be altered through the register settings. see the cdc conversion sequence time section for more information. the time required for the AD7148 to transition from a full power state to a reduced power state after the user stops touching the external sensors is configurable. the pwr_down_timeout bits in the amb_comp_ctrl0 register (address 0x002[13:12]) control the time delay before the AD7148 transitions to the reduced power state after the user stops touching the sensors. low latency from to uch to response in low power mode, the AD7148 remains in a low power state until proximity is detected on any one of the external sensors. when proximity is detected, the ad718 is automatically configured into the full power mode operation, thus converting each sequence every 36 ms. using this method, the latency delay is minimized because the AD7148 is operating in full power mode by the time the user physically makes contact with a sensor. no yes yes no timeout 07155-018 user in proximity to sensor? proximity timer count down conversion sequence every 36ms for sensor readback user in proximity to sensor? conversion sequence every lp_conv_delay update compensation logic data path AD7148 setup and initialization power_mode = 10 figure 19. low power mode operation
AD7148 rev. 0 | page 13 of 56 capacitance-to-digital converter the capacitance-to-digital converter on the AD7148 has a - architecture with 16-bit resolution. there are eight possible inputs to the cdc that are connected to the input of the converter through a switch matrix. the sampling frequency of the cdc is 250 khz. oversampling the cdc output the decimation rate, or oversampling ratio, is determined by the decimation bits of the pwr_control register (address 0x000[9:8]), as listed in table 8 . table 8. cdc decimation rate decimation bits decimation rate cdc output rate per stage (ms) 00 256 3.072 01 128 1.536 10 64 0.768 11 64 0.768 the decimation process on the AD7148 is an averaging process, during which a number of samples are taken, and the averaged result is output. due to the architecture of the digital filter used, the number of samples taken (per stage) is equal to 3 the decima- tion rate. that is, 3 256 samples or 3 128 samples are averaged to obtain each stage result. the decimation process reduces the amount of noise present in the final cdc result. however, the higher the decimation rate, the lower the output rate per stage; thus, a trade-off is possible between a noise-free signal and speed of sampling. capacitance sensor offset control there are two programmable dacs on board the AD7148 to null the effect of any stray capacitances on the cdc measurement. these offsets are due to stray capacitance to ground. best practice is to ensure that the cdc output for any stage is approximately equal to midscale (~32,700) when no sensor is active. the simplified block diagram in figure 20 shows how to apply the stagex_offset registers to null the offsets. the 6-bit pos_afe_offset and neg_afe_offset bits program the offset dac to provide 0.32 pf resolution offset adjustment over a range of 20 pf. apply the positive and negative offsets to either the positive or the negative cdc input using the neg_afe_offset and pos_afe_offset bits. this process is required only once during the initial capacitance sensor characterization. 0 7155-019 pos_afe_offset 16-bit cdc neg_afe_offset +dac (20pf range) pos_afe_offset_swap bit neg_afe_offset_swap bit 6 6 16 cin cinx_connection_setup bits ?dac (20pf range) + _ figure 20. analog front-end o ffset control conversion sequencer the AD7148 has an on-chip sequencer to implement conversion control for the input channels. up to eight conversion stages can be performed in one sequence. each of the eight conversion stages can measure the input from a different sensor. by using the bank 2 registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. for example, a slider sensor can be assigned to stage0 through stage7, or a button sensor can be assigned to stage0. for each conversion stage, the input mux that connects the cinx inputs to the converter can have a unique setting.
AD7148 rev. 0 | page 14 of 56 the AD7148 on-chip sequence controller provides conversion control, beginning with stage0. figure 21 shows a block diagram of the cdc conversion stages and cinx inputs. a conversion sequence is defined as a sequence of cdc conversions starting at stage0 and ending at the stage determined by the value that is programmed using the sequence_stage_num bits in the pwr_control register (address 0x000[7:4]). depending on the number and type of capacitance sensors that are used, not all conversion stages are required. use the sequence_ stage_num bits to set the number of conversions in one sequence, depending on the sensor interface requirements. for example, these bits are set to 0005 if the cinx inputs are mapped to only six stages. in addition, set the stagex_cal_en register according to the number of stages that are used. 07155-020 stage0 stage1 stage2 stage3 stage4 stage5 stage6 stage7 switch matrix - 16-bit adc c o n v e r s i o n s e q u e n c e cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 figure 21. cdc conversion stages the number of required conversion stages depends completely on the number of sensors attached to the AD7148. figure 22 shows how many conversion stages are required for each sensor and how many inputs to the AD7148 each sensor requires. a button sensor generally requires one sequencer stage; however, it is possible to configure two button sensors to operate differen- tially. only one button from the pair can be activated at a time; pressing both buttons together results in neither button being activated. this configuration requires one conversion stage (see figure 22 , b2 and b3). a wheel sensor requires eight stages, and a slider requires two stages. the result from each stage is used by the host software to determine user position on the slider or wheel. the algorithms that perform this process are available from analog devices, free of charge, on signing a software license. cdc conversion sequence time the time required for one complete measurement for all eight stages by the cdc is defined as the cdc conversion sequence time. the sequence_stage_num and decimation bits determine the conversion time, as shown in table 9 . for example, while operating with a decimation rate of 128, if the sequence_stage_num bits are set to 0005 for the conversion of six stages in a sequence, the conversion sequence time is 9.216 ms. 07155-021 buttons cdc cdc + ? slider cdc + ? + ? + ? cdc cdc + ? + ? cdc cdc + ? + ? cdc cdc + ? + ? cdc AD7148 sequencer b2 b3 b1 cdc + ? cdc + ? wheel stage1 stage0 stage4 stage3 AD7148 sequencer AD7148 sequencer stage0 stage1 stage1 stage1 stage1 stage1 stage1 stage1 figure 22. sequencer setup for sensors
AD7148 rev. 0 | page 15 of 56 table 9. cdc conversion times for full power mode conversion time (ms) sequence_stage_num decimation = 64 decimation = 128 decimation = 256 0 0.768 1.536 3.072 1 1.536 3.072 6.144 2 2.304 4.608 9.216 3 3.072 6.144 12.288 4 3.84 7.68 15.36 5 4.608 9.216 18.432 6 5.376 10.752 21.504 7 6.144 12.288 24.576 full power mode cdc conversion sequence time the full power mode cdc conversion sequence time for all eight stages is set by configuring the sequence_stage_num and decimation bits, as outlined in table 9 . figure 23 shows a simplified timing diagram of the full power cdc conversion time. the full power mode cdc conversion time, t conv_fp , is set using table 9 . t conv_fp conversion sequence n conversion sequence n+1 conversion sequence n+2 cdc conversion 07155-022 figure 23. full power mode cdc conversion sequence time low power mode cdc conversion sequence time with delay the frequency of each cdc conversion, while operating in the low power automatic wake-up mode, is controlled by using the lp_conv_delay bits located at address 0x000[3:2], in addi- tion to the registers listed in table 9 . this feature provides some flexibility for optimizing the conversion time to meet system requirements vs. AD7148 power consumption. for example, maximum power savings is achieved when the lp_conv_delay bits (address 0x000[3:2] are set to 11. with a setting of 11, the AD7148 automatically wakes up, performing a conversion every 800 ms. table 10. lp_conv_delay settings lp_conv_delay bits delay between conversions (ms) 00 200 01 400 10 600 11 800 figure 24 shows a simplified timing example of the low power cdc conversion time. as shown, the low power cdc conversion time is set by t conv_fp and the lp_conv_delay bits. 0 7155-023 conversion sequence n cdc conversion conversion sequence n+1 lp_conv_delay t conv_fp t conv_lp figure 24. low power mode cdc conversion sequence time cdc conversion results certain high resolution sensors require the host to read back the cdc conversion results for processing. the registers required for host processing are located in the bank 3 registers. the host processes the data readback from these registers using a software algorithm to determine position information. in addition to the results registers found in the bank 3 registers, the AD7148 provides the 16-bit cdc output data directly, starting at address 0x00b of the bank 1 registers. reading back the cdc 16-bit conversion data register allows for customer-specific appli- cation data processing.
AD7148 rev. 0 | page 16 of 56 capacitance sensor input configuration each input connection from the external capacitance sensors to the AD7148 converter can be uniquely configured by using the registers in bank 2 (see tabl e 39 through table 42 ). these registers are used to configure input pin connection setups, sensor offsets, sensor sensitivities, and sensor limits for each stage. each sensor can be individually optimized. for example, a button sensor connected to stage0 can have different sensitivity and offset values from those of a button with a different function that is connected to a different stage. cinx input multiplexer setup the cinx_connection_setup register bits provide options for connecting the sensor input pins to the cdc (see tabl e 39 and table 40 ). the AD7148 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. each input pin can be tied to either the negative or the positive input of the cdc, or it can be left floating. each input can also be internally connected to the bias signal to help prevent cross coupling. if an input is not used, always connect it to bias. connecting a cinx input pin to the positive cdc input results in an increase in cdc output code when the corresponding sensor is activated. connecting a cinx input pin to the negative cdc input results in a decrease in cdc output code when the corre- sponding sensor is activated. the AD7148 performs a sequence of eight conversions. the multiplexer can have different connection settings for each of the eight conversions by using the cinx_connection_ setup bits. for example, cin0 can be connected to the negative cdc input or left floating. the same holds true for all eight conversion stages. two bits in each sequence stage register control the mux setting for the input pin, as shown in figure 25 . single-ended connections to the cdc a single-ended connection to the cdc is defined as having one cinx input connected to either the positive or the negative cdc input. a differential connection to the cdc is defined as having one cinx input connected to the positive cdc input and a second cinx input connected to the negative input of the cdc. when a single-ended connection to the cdc is made in any stage, the se_connection_setup bits in the stagex_ connection_setup registers should be applied. these bits ensure that, during a single-ended connection to the cdc, the input paths to both terminals are matched. this matching of input paths, in turn, improves the power supply rejection of the converter measurement. table 11. application of se_connection_setup bits bit values description 00 do not use. 01 single-ended connection. for this stage, there is one cinx connected to the positive cdc input. 10 single-ended connection. for this stage, there is one cinx connected to the negative cdc input. 11 differential connection. for this stage, there is one cinx connected to the negative cdc input and one cinx connected to the positive cdc input. if more than one cinx input is connected to either the positive or negative input of the converter for the same conversion, set se_connection_setup = 11. for example, if cin0 and cin3 are connected to the positive input of the cdc, se_connection_setup = 11. 0 7155-024 cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 cin setting cinx_connection _setup bits 00 cinx floating 01 cinx connected to negative cdc input 10 cinx connected to positive cdc input 11 cinx connected to bias cdc ? + figure 25. input mux configuration options
AD7148 rev. 0 | page 17 of 56 noncontact proximity detection the AD7148 internal signal processing continuously monitors all capacitance sensors for noncontact proximity detection. this feature provides the ability to detect when a user is approaching a sensor, at which time all internal calibration is immediately disabled while the AD7148 is automatically configured to detect a valid contact. the proximity control register bits are described in table 12 . the fp_proximity_cnt and lp_proximity_cnt register bits (address 0x002[11:4]) control the length of the calibration disable period after the user leaves the sensor and proximity is no longer active in full and low power modes. the calibration is disabled during this time and is enabled again at the end of this period, provided that the user is no longer approaching, or in contact with, the sensor. figure 26 and figure 27 show examples of how these registers are used to set the full and low power mode calibration disable periods. the calibration disable period in full power mode is equal to fp_proximity_cnt 16 time taken for one conversion sequence in full power mode. the calibration disable period in low power mode is equal to lp_proximity_cnt 4 time taken for one conversion sequence in low power mode. table 12. proximity control registers (see figure 30 ) bits length register address description fp_proximity_cnt 4 bits 0x002[7:4] calibration disable time in full power mode. lp_proximity_cnt 4 bits 0x002[11:8] calibration disable time in low power mode. fp_proximity_recal 10 bits 0x004[9:0] full power mode proximity recalibration time. lp_proximity_recal 6 bits 0x004[15:10] low power mode proximity recalibration time. proximity_recal_lvl 8 bits 0x003[7:0] proximity recalibration level. this value, multiplied by 16, controls the sensitivity of comparator 2 in figure 30 . proximity_detection_rate 6 bits 0x003[13:8] proximity detection rate. this value, multiplied by 16, controls the sensitivity of comparator 1 in figure 30 . proximity detection (internal) calibration (internal) 12345 678910111213141516 cdc conversion sequence (internal) 07155-025 calibration enabled calibration disabled t conv_fp user leaves sensor area here user approaches sensor here t caldis figure 26. full power mode proximity detection example with fp_proximity_cnt = 1 07155-026 notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay 2. proximity is set when user approaches the sensor at which time the internal calibration is disabled. 3. t caldis = ( t conv_lp lp_proximity_cnt 4) calibration enabled calibration disabled proximity detection (internal) calibration (internal) t caldis t conv_lp 12345678910111213141516 cdc conversion sequence (internal) user leaves sensor area here user approaches sensor here 1718 19 20 21 2223 24 figure 27. low power mode proximity detection with lp_proximity_cnt = 4
AD7148 rev. 0 | page 18 of 56 recalibration in certain situations, the proximity flag can be set for a long period: for example, when a user hovers over a sensor for a long time. the environmental calibration on the AD7148 is suspended while proximity is detected, but changes may occur to the ambient capacitance level during the proximity event. this means that the ambient value stored on the AD7148 no longer represents the actual ambient value. in this case, even when the user has left the sensor, the proximity flag may still be set. this situation could occur if user interaction creates some moisture on the sensor, causing the new sensor ambient value to be different from the expected value. in this situation, the AD7148 automatically forces an internal recalibration, ensuring that the ambient values are recalibrated, regardless of how long the user hovers over a sensor. the recalibration ensures maximum sensor performance. the AD7148 recalibrates automatically when the measured cdc value exceeds the stored ambient value by an amount determined by the proximity_recal_lvl bits (address 0x003[7:0]) for a set period of time, known as the recalibration timeout. in full power mode, the recalibration timeout is controlled by fp_proximity_recal; in low power mode, the timeout is controlled by lp_proximty_recal. the recalibration timeout in full power mode is the value of the fp_proximity_recal multiplied by the time taken for one conversion sequence in full power mode. the recalibration timeout in low power mode is the value of the lp_proximity_recal multiplied by the time taken for one conversion sequence in low power mode. figure 28 and figure 29 show examples of how the fp_ proximity_recal and lp_proximity_recal register bits (address 0x004[15:0]) control the timeout period before a recalibration while operating in the full power and low power modes. these figures show a user approaching a sensor, followed by the user leaving the sensor while the proximity detection remains active after the user leaves the sensor. the measured cdc value exceeds the stored ambient value by the amount set in the proximity_ recal_lvl bits for the entire timeout period. the sensor is automatically recalibrated at the end of the timeout period. calibration enabled t recal_timeout 16 30 70 t conv_fp measured cdc value > stored ambient by proximity_recal _lvl recalibration time-out proximity detection (internal) calibration (internal) c dc conversion sequence (internal) recalibration counter (internal) 07155-027 notes 1. sequence conversion time t conv_fp determined from table 9. 2. t caldis = t conv_fp fp_proximity_cnt 16. 3. t recal_timeout = t conv_fp fp_proximity_recal. 4. t recal = 2 t conv_fp . user approaches sensor here user leaves sensor area here t caldis t recal calibration disabled figure 28. full power mode proximity detection with forced reca libration example with fp_proximity_cnt = 1 and fp_proximity_rec al = 40
AD7148 rev. 0 | page 19 of 56 07155-028 notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay 2. t caldis = t conv_lp lp_proximity_cnt 4 3. t recal_timeout = t conv_fp lp_proximity_recal 4. t recal = 2 t conv_lp calibration enabled t recal_timeout 16 30 70 t conv_lp recalibration time-out proximity detection (internal) calibration (internal) c dc conversion sequence (internal) recalibration (internal) user approaches sensor here user leaves sensor area here measured cdc value > stored ambient by proximity_recal _lvl t recal t caldis calibration disabled figure 29. low power mode proximity detection with forced recalibration example with lp_proximity_cnt = 4 and lp_proximity_reca l = 40
AD7148 rev. 0 | page 20 of 56 proximity sensitivity the fast filter in figure 30 is used to detect when someone is close to the sensor (proximity). two conditions set the internal proximity detection signal, using comparator 1 and comparator 2. comparator 1 detects when a user is approaching a sensor. the proximity_detection_rate bits (address0x003[13:8]) controls the sensitivity of comparator 1. for example, if proximity_detection_rate is set to 4, the proximity 1 signal is set when the absolute difference between word1 and word3 exceeds (4 16) lsb codes. comparator 2 detects when a user hovers over a sensor or approaches a sensor very slowly. the proximity_recal_lvl bits (address 0x003[7:0]) control the sensitivity of comparator 2. for example, if proximity_ recal_lvl is set to 75, the proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds (75 16) lsb codes. ff_skip_cnt the proximity detection fast fifo is used by the on-chip logic to determine if proximity is detected . the fast fifo expects to receive samples from the converter at a set rate. ff_skip_cnt (register 0x002[3:0]) is the fast filter skip control, which used to normalize the frequency of the samples going into the fifo, regardless of how many conversion stages are in a sequence. this value determines which cdc samples are not used (skipped) in the proximity detection fast fifo. determining the ff_skip_cnt value is required only once during the initial setup of the capacitance sensor interface. table 13 shows how ff_skip_cnt controls the update rate to the fast fifo. recommended value for this setting, when using all eight conversion stages on the AD7148, is ff_skip_cnt = 0000 = no samples skipped. 07155-029 8 7 n = 0 proximity_detection_rate register 0x003 proximity_recal_lvl register 0x003 bank 3 registers proximity 2 slow_filter_update_lvl register 0x003 bank 3 registers sw1 16 notes 1. slow_filter_en is set and sw1 is closed when |stagex_sf_ word0?stagex_sf_word 1 | exceeds the value programmed in the slow_filter_update_lvl bits providing proximity is not set. 2. proximity 1 is set when |stagex_ff_ word0? stagex_ff_word3 | exceeds the value programmed in the proximity_detection_rate bits. 3. proximity 2 is set when | average?ambient | exceeds the value programmed in the proximity_recal_lvl bits. 4. description of comparator functions: comparator 1: used to detect when a user is approaching or leaving a sensor. comparator 2: used to detect when a user is hovering over a sensor or approaching a sensor very slowly. fp_proximity_recal register 0x004 lp_proximity_recal register 0x004 proximity ambient value stagex_sf_wordx cdc output code time sensor contact stagex_sf_ambient bank 3 registers stagex_ff_avg bank 3 registers fp_proximity_cnt register 0x002 lp_proximity_cnt register 0x002 proximity 1 proximity timing control logic word( n ) stagex_sf_word7 stagex_sf_word6 stagex_sf_word5 stagex_sf_word4 stagex_sf_word3 stagex_sf_word2 stagex_sf_word1 stagex_sf_word0 stagex_ff_wordx also used to detect if the sensor ambient level has changed as a result of user interaction. for example, humidity or dirt left behind on sensor. comparator 3: used to enable the slow filter update rate. the slow filter is updated when slow_filter_en is set and proximity is not set. word0 ? word3 cdc stagex_ff_word0 stagex_ff_word1 stagex_ff_word2 stagex_ff_word3 stagex_ff_word4 stagex_ff_word5 stagex_ff_word6 stagex_ff_word7 average ? ambient proximity comparator 1 comparator 2 comparator 3 slow_filter_en word0 ? cdc value figure 30. proximity detection logic
AD7148 rev. 0 | page 21 of 56 table 13. ff_skip_cnt settings fast fifo update rate ff_ skip_ cnt decimation = 64 decimation = 128 decimation = 256 0 0.768 (sequence_stage_num + 1) ms 1.536 (sequence_stage_num + 1) ms 3.072 (sequence_stage_num + 1) ms 1 1.536 (sequence_stage_num + 1) ms 3.072 (sequence_stage_num + 1) ms 6.144 (sequence_stage_num + 1) ms 2 2.3 (sequence_stage_num + 1) ms 4.608 (sequence_stage_num + 1) ms 9.216 (sequence_stage_num + 1) ms 3 3.072 (sequence_stage_num + 1) ms 6.144 (sequence_stage_num + 1) ms 12.288 (sequence_stage_num + 1) ms 4 3.84 (sequence_stage_num + 1) ms 7.68 (sequence_stage_num + 1) ms 15.36 (sequence_stage_num + 1) ms 5 4.6 (sequence_stage_num + 1) ms 9.216 (sequence_stage_num + 1) ms 18.432 (sequence_stage_num + 1) ms 6 5.376 (sequence_stage_num + 1) ms 10.752 (sequence_stage_num + 1) ms 21.504 (sequence_stage_num + 1) ms 7 6.144 (sequence_stage_num + 1) ms 12.288 (sequence_stage_num + 1) ms 24.576 (sequence_stage_num + 1) ms 8 6.912 (sequence_stage_num + 1) ms 13.824 (sequence_stage_num + 1) ms 27.648 (sequence_stage_num + 1) ms 9 7.68 (sequence_stage_num + 1) ms 15.36 (sequence_stage_num + 1) ms 30.72 (sequence_stage_num + 1) ms 10 8.448 (sequence_stage_num + 1) ms 16.896 (sequence_stage_num + 1) ms 33.792 (sequence_stage_num + 1) ms 11 9.216 (sequence_stage_num + 1) ms 18.432 (sequence_stage_num + 1) ms 36.864 (sequence_stage_num + 1) ms 12 9.984 (sequence_stage_num + 1) ms 19.968 (sequence_stage_num + 1) ms 39.936 (sequence_stage_num + 1) ms 13 10.752 (sequence_stage_num + 1) ms 21.504 (sequence_stage_num + 1) ms 43.008 (sequence_stage_num + 1) ms 14 11.52 (sequence_stage_num + 1) ms 23.04 (sequence_stage_num + 1) ms 46.08 (sequence_stage_num + 1) ms 15 12.288 (sequence_stage_num + 1) ms 24.576 (sequence_stage_num + 1) ms 49.152 (sequence_stage_num + 1) ms
AD7148 rev. 0 | page 22 of 56 environmental calibration the AD7148 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels. capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. the AD7148 achieves optimal and reliable sensor performance by continuously monitoring the cdc ambient levels and correcting for any changes by adjusting the stagex_ high_threshold and stagex_low_threshold register values, as described in equation 1 and equation 2. the cdc ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in contact with the sensor. the compensation logic runs automatically on every conversion after configuration when the AD7148 is not being touched, which allows the AD7148 to account for rapidly changing environmental conditions. the ambient compensation control registers give the host access to general setup and controls for the compensation algorithm. on-chip ram stores the compensation data for each conversion stage, as well as setup information specific to each stage. figure 31 shows an example of an ideal capacitance sensor behavior where the cdc ambient level remains constant, regardless of the environmental conditions. the cdc output shown is for a pair of differential button sensors, where one sensor caused an increase and the other caused a decrease in measured capacitance when activated. the positive and negative sensor threshold levels are calculated as a percentage of the stagex_offset_high and stagex_offset_low values based on the threshold sensitivity settings and the ambient value. these values are sufficient to detect a sensor contact, resulting in the AD7148 asserting the int output when threshold levels are exceeded. cdc output codes t stagex_low_threshold stagex_high_threshold cdc ambient value changing environmental conditions 07155-030 sensor 1 int asserted sensor 2 int asserted figure 31. ideal sensor behavior with a constant ambient level capacitance sensor behavior without calibration figure 32 shows the typical behavior of a capacitance sensor with no applied calibration. this figure shows ambient levels drifting over time as environmental conditions change. the ambient level drift results in the detection of a missed user contact on sensor 2. this is a result of the initial low offset level remaining constant while the ambient levels drifted upward beyond the detection range. 07155-031 cdc output codes t cdc ambient value drifting sensor 1 int asserted sensor 2 int not asserted changing environmental conditions stagex_high_threshold stagex_low_threshold figure 32. typical sensor behavior without calibration applied the capacitance sensor behavior with calibration section describes how the AD7148 adaptive calibration algorithm prevents errors such as this from occurring. capacitance sensor behavior with calibration the AD7148 on-chip adaptive calibration algorithm prevents sensor detection errors such as the one shown in figure 32 . error prevention is accomplished by monitoring cdc ambient levels and readjusting the initial stagex_offset_high and stagex_offset_low values according to the amount of ambient drift measured on each sensor. the internal stagex_ high_threshold and stagex_low_threshold values described in equation 1 and equation 2 are automatically updated based on the new values of stagex_offset_high and stagex_offset_low. this closed-loop routine ensures the reliability and repeatable operation of every sensor connected to the AD7148 under dynamic environmental conditions. figure 33 shows a simplified example of how the AD7148 applies the adaptive calibration process resulting in no interrupt errors under changing cdc ambient levels due to environmental conditions.
AD7148 rev. 0 | page 23 of 56 07155-032 cdc output codes t sensor 1 int asserted 1 2 3 4 5 6 stagex_high_threshold (postcalibrated register value) changing environmental conditions notes 1. initial stagex_offset_high register value. 2. postcalibrated register stagex_high_threshold. 3. postcalibrated register stagex_high_threshold. 4. initial stagex_low_threshold. 5. postcalibrated register stagex_low_threshold. 6. postcalibrated register stagex_low_threshold. cdc ambient value drifting stagex_low_threshold (postcalibrated register value) sensor 2 int asserted figure 33. typical sensor behavior with calibration applied on the data path slow fifo as shown in figure 30 , there are a number of fifos implemented on the AD7148. these fifos are located in bank 3 of the on-chip memory. the slow fifos are used by on-chip logic to monitor the ambient capacitance level from each sensor. avg_fp_skip and avg_lp_skip in register 0x001, bits[13:12]are the slow fifo skip control for full power mode, avg_fp_skip. bits[15:14] in the same register are the slow fifo skip control for low power mode, avg_lp_skip. these values determine which cdc samples are not used (skipped) in the slow fifo. changing theses values slows down or speeds up the rate at which the ambient capacitance value tracks the measured capacitance value read by the converter. slow fifo update rate in full power mode is equal to avg_fp_skip [(3 decimation rate) (sequence_stage_num +1) (ff_skip_cnt +1) 4x10 ?7 ] slow fifo update rate in low power mode is equal to (avg_lp_skip +1) [(3 decimation rate) (sequence_stage_num +1) (ff_skip_cnt +1) 4x10 ?7 ]/[(ff_skip_cnt +1 ) + lp_conv_delay] the slow fifo is used by the on-chip logic to track the ambient capacitance value. the slow fifo expects to receive samples from the converter at a rate of 25 ms. avg_fp_skip and avg_lp_ skip are used to normalize the frequency of the samples going into the fifo, regardless of how many conversion stages are in a sequence. determining the avg_fp_skip and avg_lp_skip values is required only once during the initial setup of the capacitance sensor interface. when using all eight conversion stages, recommended values for these settings are avg_fp_skip = 00 = skip 3 samples avg_lp_skip = 00 = skip 0 samples slow_filter_update_lvl the slow_filter_update_lvl (address 0x003[15:14]) controls whether the most recent cdc measurement goes into the slow fifo (slow filter) or not. the slow filter is updated when the difference between the current cdc value and last value pushed into the slow fifo is greater than slow_filter_ update_lvl. equations for on-chip logic stage high an d logic stage low threshold calculation stagex_high_threshold = stage_sf_ambient + ? ? ? ? ? ? 4 __ high offset stagex + ? ? ? ? ? ? ? ? ? ? ? ? ? 16 4 __ __ high offset stagex high offset stagex pos_threshold_sensitivity (1) stagex_low_threshold = stage_sf_ambient + ? ? ? ? ? ? 4 __ low offset stagex + ? ? ? ? ? ? ? ? ? ? ? ? ? 16 4 __ __ low offset stagex low offset stagex pos_threshold_sensitivity (2)
AD7148 rev. 0 | page 24 of 56 adaptive threshold and sensitivity the AD7148 provides an on-chip self-learning adaptive threshold and sensitivity algorithm. this algorithm continuously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user. as a result, the AD7148 maintains optimal threshold and sensitivity levels for all types of users, regardless of finger size. the threshold level is always referenced from the ambient level and is defined as the cdc converter output level that must be exceeded for a valid sensor contact. the sensitivity level is defined as how sensitive the sensor is before a valid contact is registered. figure 34 provides an example of how the adaptive threshold and sensitivity algorithm works. the positive and negative sensor threshold levels are calculated as a percentage of the stagex_ offset_high and stagex_offset_low values, based on the threshold sensitivity settings and the ambient value. on configuration, initial estimates are supplied for both stagex_ offset_high and stagex_offset_low, after which the calibration engine automatically adjusts the stagex_high_ threshold and stagex_low_threshold values for sensor response. the AD7148 tracks the average maximum and minimum values measured from each sensor. these values give an indication of how the user is interacting with the sensor. a large finger gives a large average maximum or minimum value, and a small finger gives smaller values. when the average maximum or minimum value changes, the threshold levels are rescaled to ensure that the threshold levels are appropriate for the current user. figure 35 shows how the minimum and maximum sensor responses are tracked by the on-chip logic. reference a in figure 34 shows an undersensitive threshold level for a small finger user, demonstrating the disadvantages of a fixed threshold level. by enabling the adaptive threshold and sensitivity algorithm, the positive and negative threshold levels are determined by the pos_threshold_sensitivity and neg_threshold_ sensitivity values and the most recent average maximum sensor output value. these bits can be used to select 16 different positive and negative sensitivity levels ranging between 25% and 95.32% of the most recent average maximum output level referenced from the ambient value. the smaller the sensitivity percentage setting, the easier it is to trigger a sensor activation. reference b shows that the positive adaptive threshold level is set at almost mid-sensitivity with a 62.51% threshold level by setting pos_threshold_sensitivity = 1000. figure 34 also provides a similar example for the negative threshold level with neg_threshold_sensitivity = 0011. ambient level cdc output codes average max value stagex_offset_high 25% 95.32% 62.51% = pos adaptive threshold level 25% 62.51% = pos adaptive threshold level 95.32% neg adaptive threshold level = 39.08% 25% 95.32% 25% 95.32% sensor contacted by small finger a verage max value stagex_offset_low neg adaptive threshold level = 39.08% sensor contacted by large finger 07155-033 stagex_offset_high is updated stagex_offset_high is updated here stagex_offset_low is updated here stagex_offset_low is updated here a b figure 34. threshold sensitivity example with pos_threshol d_sensitivity = 1000 and neg_ threshold_sensitivity = 0011
AD7148 rev. 0 | page 25 of 56 07155-034 - 16-bit cdc 16 stagex_max_word0 stagex_max_word1 stagex_max_word2 stagex_max_word3 stagex_max_avg bank 3 registers stagex_high_threshold bank 3 registers stagex_max_temp bank 3 registers bank 3 registers stagex_min_word0 stagex_min_word1 stagex_min_word2 stagex_min_word3 stagex_min_avg bank 3 register3 stagex_low_threshold bank 3 registers stagex_min_temp bank 3 registers bank 3 registers max level detection logic min level detection logic figure 35. tracking the minimum and maximum average sensor values table 14. additional information about environmental calibration and adaptive threshold registers bit register location description neg_threshold_sensitivity bank 2 used in equation 2. this value is programmed once at startup. neg_peak_detect bank 2 used by internal adaptive threshold logic only. the neg_peak_detect is set to a percentage of the difference between the ambient cdc value and the minimum average cdc value. if the output of the cdc gets within the neg_peak_detect percentage of the min imum average, only then is the minimum average value updated. pos_threshold_sensitivity bank 2 used in equation 1. this value is programmed once at startup. pos_peak_detect bank 2 used by internal adaptive threshold logic only. the pos_peak_detect is set to a percentage of the difference between the ambient cdc value and the maximum average cdc value. if the output of the cdc gets within the pos_peak_detect percentage of the maximum average, only then is the maximum average value updated. stagex_offset_low bank 2 used in equation 2. an initial value (based on sensor characterization) is programmed into this register at startup. the AD7148 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. set to 80% of the stagex_offset_low_clamp value. stagex_offset_high bank 2 used in equation 1. an initial value (based on sensor characterization) is programmed into this register at startup. the AD7148 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. set to 80% of the stagex_offset_high_clamp value. stagex_offset_high_clamp bank 2 used by internal environmen tal calibration and adaptive threshold algorithms only. an initial value (based on sensor characteriza tion) is programmed into this register at startup. the value in this register prevents a user from causing sensor output value to exceed the expected nominal value. set to the maximum expected sensor response, maximum change in cdc output code. stagex_offset_low_clamp bank 2 used by internal environmenta l calibration and adaptive threshold algorithms only. an initial value (based on sensor characteriza tion) is programmed into this register at startup. the value in this register prevents a user from causing sensor output value to exceed the expected nominal value. set to the minimum expected sensor response, minimum change in cdc output code . stagex_sf_ambient bank 3 used in equation 1 and equation 2. this is the ambient sensor output, when the sensor is not touched, as calcul ated using the slow fifo. stagex_high_threshold bank 3 equation 1 value. stagex_low_threshold bank 3 equation 2 value.
AD7148 rev. 0 | page 26 of 56 interrupt output the AD7148 has an interrupt output that triggers an interrupt service routine on the host processor. the int signal is on pin 12 and is an open-drain output. there are two types of interrupt events on the AD7148: a cdc conversion complete interrupt and a sensor threshold interrupt. each interrupt has enable and status registers. the conversion complete and sensor threshold interrupts can be enabled on a per conversion stage basis. the status registers indicate what type of interrupt triggered the int pin. status registers are cleared, and the int signal is reset high during a read operation. the signal returns high as soon as the read address is set up. cdc conversion-complete interrupt the AD7148 interrupt signal asserts low to indicate the completion of a conversion stage, and new conversion result data is available in the registers. the interrupt can be independently enabled for each conversion stage. each conversion-stage-complete interrupt can be enabled via the stagex_complete_int_en register (address 0x007). this register has a bit that corresponds to each conversion stage. setting this bit to 1 enables the interrupt for that stage. clearing this bit to 0 disables the conversion complete interrupt for that stage. in normal operation, the interrupt is enabled only for the last stage in a conversion sequence. for example, if there are five conversion stages, the conversion-complete interrupt for stage4 is enabled. int asserts only when all five conversion stages are complete, and the host can read new data from all five results registers. the inter- rupt is cleared by reading the stagex_complete_int_ status register located at address 0x00a. register 0x00a is the conversion-complete interrupt status register. each bit in this register corresponds to a conversion stage. if a bit is set, it means that the conversion-complete interrupt for the corresponding stage has been triggered. this register is cleared on a read, provided that the underlying condition that triggered the interrupt has gone away. sensor touch interrupt the sensor touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. configuring the AD7148 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. the second interrupt is required to alert the host processor that the user is no longer contacting the sensor. the registers located at address 0x005 (stagex_low_int_en) and address 0x006 (stagex_high_int_en) are used to enable the interrupt output for each stage. the registers located at address 0x008 (stagex_low_limit_int) and address 0x009 (stagex_high_limit_int) are used to read back the interrupt status for each stage. figure 36 shows the interrupt output timing during contact with one of the sensors connected to stage0 while operating in the sensor touch interrupt mode. for a low limit configuration, the interrupt output is asserted as soon as the sensor is contacted and again after the user has stopped contacting the sensor. note that the interrupt output remains low until the host processor reads back the interrupt status registers located at address 0x008 and address 0x009. the interrupt output is asserted when there is a change in the threshold status bits. this change indicates that a user is now touching the sensor(s) for the first time, the number of sensors being touched has changed, or the user is no longer touching the sensor(s). reading the status bits in the interrupt status register shows the current sensor activations. 4 2 conversion stage serial readback notes: 1. user touching down on sensor 2. addr ess 0x008 read back to clear interrupt 3. user lifting off of sensor 4. addr ess 0x008 read back to clear interrupt stage0 stage1 int output 07155-035 figure 36. example of sensor touch interrupt
AD7148 rev. 0 | page 27 of 56 ac shield output the AD7148 measures capacitance between cinx and ground. any capacitance to ground on the signal path between the cinx pins and the sensor is included in the conversion result. to eliminate the stray capacitance to ground, the ac shield signal should be used to shield the connection between the sensor and cinx, as shown in figure 37 . the plane around the sensors should also be connected to ac shield . the ac shield output is the same signal waveform as the excita- tion signal on cinx. therefore, there is no ac current between cinx and ac shield , and any capacitance between these pins does not affect the cinx charge transfer. using ac shield eliminates capacitance-to-ground pick-up, which means that the AD7148 can be placed up to 60 cm away from the sensors. this allows the AD7148 to be placed on a separate pcb from the sensors, provided that the connections between the sensors and the cinx inputs are correctly shielded, using ac shield . sensor pcb AD7148 ac shield cin0 cin1 cin2 cin3 07155-036 figure 37. ac shield
AD7148 rev. 0 | page 28 of 56 i 2 c-compatible serial interface the AD7148 supports the industry standard 2-wire i 2 c serial inter- face protocol. the two wires associated with the i 2 c timing are the sclk and the sda inputs. the sda is an i/o pin that allows both register write and register readback operations. the AD7148 is always a slave device on the i 2 c serial interface bus. it has a single fixed 7-bit device address, address 0101 110. the AD7148 responds when the master device sends its device address over the bus. the AD7148 cannot initiate data transfers on the bus. table 15. AD7148 i 2 c device address dev a6 dev a5 dev a4 dev a3 dev a2 dev a1 dev a0 0 1 1 0 1 1 0 data transfer data is transferred over the i 2 c serial interface in 8-bit bytes. the master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, sda, while the serial clock line, sclk, remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the direction of the data transfer. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from, or written to it. if the r/ w bit is a 0, the master writes to the slave device. if the r/ w bit is a 1, the master reads from the slave device. data is sent over the serial bus in a sequence of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high can be interpreted as a stop signal. the number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes are read or written, a stop condition is estab- lished. a stop condition is defined by a low-to-high transition on sda, while sclk remains high. if the AD7148 encounters a stop condition, it returns to its idle condition, and the address pointer register resets to address 0x00. writing data over the i 2 c bus the process for writing to the AD7148 over the i 2 c bus is shown in figure 38 and figure 40 . the device address is sent over the bus followed by the r/ w bit set to 0. this is followed by two bytes of data that contain the 10-bit address of the internal data register to be written. the following bit map shows the upper register address bytes. note that bit 7 to bit 2 in the upper address byte are dont care bits. the address is contained in the 10 lsbs of the register address bytes. msb lsb 7 6 5 4 3 2 1 0 x x x x x x register address bit 9 register address bit 8 the following bit map shows the lower register address bytes. msb lsb 7 6 5 4 3 2 1 0 reg add reg add reg add reg add reg add reg add reg add reg add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the third data byte contains the eight msbs of the data to be written to the internal register. the fourth data byte contains the eight lsbs of data to be written to the internal register. the AD7148 address pointer register automatically increments after each write, allowing the master to sequentially write to all registers on the AD7148-1 in the same write transaction. however, the address pointer register does not wrap around after the last address. any data written to the AD7148 after the address pointer has reached its maximum value is discarded. all registers on the AD7148 have 16 bits. two consecutive 8-bit data bytes are combined and written to the 16-bit registers. to avoid errors, all writes to the device must contain an even number of data bytes. to finish the transaction, the master generates a stop condition on sdo or generates a repeat start condition if the master is to maintain control of the bus. reading data over the i 2 c bus to read from the AD7148, the address pointer register must first be set to the address of the required internal register. the master performs a write transaction and writes to the AD7148 to set the address pointer. the master then outputs a repeat start condition to keep control of the bus or, if this is not possible, ends the write transaction with a stop condition. a read transaction is initiated, with the r/ w bit set to 1. the AD7148 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. this operation is shown in figure 39 and figure 40 . because the address pointer automatically increases after each read, the AD7148 continues to output readback data until the master puts a no acknowledge and a stop condition on the bus. if the address pointer reaches its maximum value, and the master continues to read from the part, the AD7148 repeatedly sends data from the last register addressed.
AD7148 rev. 0 | page 29 of 56 notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. 7-bit device address [dev a6:dev a0] = [0 1 0 1 1 x x], where x are don't care bits. 4. 16-bit register address[a15:a0] = [x, x, x, x, x, x, a9, a8 , a7, a6, a5, a4, a3, a2, a1, a0], where x are don?t care bits. 5. register address [a15:a8] and register address [a7:a0] are always separated by a low ack bit. 6. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 start AD7148 device address a9 a8 register address[a15:a8] register address[a7:a0] ack d15 d14 d9 d8 35 27 28 29 34 37 36 43 38 44 d1 d0 d7 d6 register data[d15:d8 ] register data[d7:d0] ack ack 45 46 ack stop dev a6 dev a5 dev a4 123 start t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 AD7148 device address 07155-037 figure 38. example of i 2 c timing for single register write operation 07155-038 notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. the master generates the ack at the end of the readback to signal that it does not want additional data. 4. 7-bit device address [dev a6:dev a0] = [0 1 0 1 1 x x], where the two lsb x's are don't care bits. 5. 16-bit register addr ess[a15:a0] = [x, x, x, x, x, x, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0], where the upper lsb x?s are don?t care bits. 6. register address [a15:a8] and register addr ess [a7:a0] are always sep arated by a low ack bit. 7. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. 8. the r/w bit is set to a1 to indicate a readback operation. sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 start AD7148-1 device address a9 a8 register addr ess[a15:a8] register addr ess[a7:a0] ack 35 28 30 34 37 36 44 38 45 d1 d0 d7 d6 register data[d7:d0] sr ack 46 p dev a6 dev a5 dev a4 1 23 t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 AD7148 device address ack 27 AD7148-1 device address dev a6 dev a5 dev a1 dev a0 r/w 29 39 35 28 30 34 37 36 44 38 45 d1 d0 d7 d6 register data[d7:d0] s ack 46 p t 5 t 4 ad7142-1 device address dev a6 dev a5 dev a1 dev a0 r/w 29 39 p using repeated start separate read and w rite transactions ack ack figure 39. example of i 2 c timing for single regi ster readback operation
AD7148 rev. 0 | page 30 of 56 ack write output from master output from ad7142 s p p ack 6-bit device address s = start bit p = stop bit sr = repeated start bit ack = acknowledge bit ack = no acknowledge bit register addr [15:8] register addr [7:0] write data high byte [15:8] write data low byte [7:0] write data high byte [15:8] write data low byte [7:0] ack read data high byte [15:8] read data low byte [7:0] ack w ack ack ack ack read (using repeated start) s ack 6-bit device address register addr high byte register addr low byte 6-bit device address read data high byte [15:8] ack w ack ack read data low byte [7:0] 07155-039 r sr p ack read data high byte [15:8] read data low byte [7:0] ack read (write transaction sets up register address) s ack 6-bit device address register addr high byte register addr low byte 6-bit device address read data high byte [15:8] ack w ack ack read data low byte [7:0] r p s ack ack figure 40. example of sequential i 2 c write and readback operation v drive input the supply voltage to all pins associated with the i 2 c serial interface (sclk, sda) is separate from the main v cc supplies and is connected to the v drive pin. this arrangement allows the AD7148 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7148 without the need for external level-shifters. the v drive pin can be connected to voltage supplies as low as 1.65 v and as high as v cc .
AD7148 rev. 0 | page 31 of 56 pcb design guidelines capacitive sensor board me chanical specifications table 16. parameter symbol min typ max unit distance from edge of any sensor to edge of grounded metal object d 1 0.1 mm distance between sensor edges 1 d 2 = d 3 = d 4 0 mm distance between bottom of sensor board and controller board or grounded metal casing 2 d 5 1.0 mm 1 the distance is dependent on the application and the positioning of the switches relative to each other and with respect to th e users finger posi tioning and handling. adjacent sensors, with 0 minimum space betw een them, are impleme nted differentially. 2 the 1.0 mm specification is meant to prev ent direct sensor board contact with any co nductive material. this specification does not guarantee no emi coupling from the controller board to the sensors. address potential emi coupling issues by placing a grounded metal shield between the capac itive sensor board and the main controller board, as shown in figure 43. 07155-040 slider buttons capacitive sensor printed circuit d 1 d 3 d 4 8-way switch metal object d 2 figure 41. capacitive sensor board mechanicals top view d 5 controller printed circuit board or metal casing 0 7155-041 capacitive sensor board figure 42. capacitive sensor board mechanicals side view capacitive sensor board d 5 controller printed circuit board or metal casing grounded metal shield 07155-042 figure 43. capacitive sensor board with grounded shield chip scale packages the lands on the chip scale package (cp-16-13) are rectangular. the printed circuit board pad for this package should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. center the land on the pad to maximize the solder joint size. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. to avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the printed circuit board. thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. connect the printed circuit board thermal pad to gnd.
AD7148 rev. 0 | page 32 of 56 power-up sequence when the AD7148 is powered up, the following sequence is recommended when initially developing the AD7148 and host microprocessor serial interface: 1. turn on the power supplies to the AD7148. 2. write to the bank 2 registers at address 0x080 through address 0x0bf. these registers are contiguous, so a sequential register write sequence can be applied. note that the bank 2 register values are unique for each application. register values come from characterization of the sensor in the application and may be provided by analog devices after the sensor board has been developed. 3. write to the bank 1 registers at address 0x000 through address 0x007, as outlined in the following list. caution at this time, address 0x001 must remain set to default value 0x0000 during this contiguous write operation. register values: address 0x000 = 0x0b2 address 0x001 = 0x000 address 0x002 = 0x3230 (depends on number of conversion stages used) address 0x003 = 0x0419 address 0x004 = 0x0832 address 0x005 = interrupt enable register; depends on required interrupt behavior address 0x006 = interrupt enable register; depends on required interrupt behavior address 0x007 = interrupt enable register; depends on required interrupt behavior 4. write to the bank 1 register, address 0x001 = 0x00ff; depends on number of conversion stages used. 5. read back the corresponding interrupt status register at address 0x008, address 0x009, or address 0x00a. the address to be read back is determined by the interrupt output configuration, as explained in the interrupt output section. 6. note that the specific registers required to be read back depend on each application. for buttons, the interrupt status registers are read back, while other sensors read data back according to the requirements of the slider or wheel algorithm. analog devices provides this informa- tion after the sensor board has been developed. 7. repeat step 5 every time int is asserted. 07155-043 first conversion sequence conversion stage AD7148 interrupt power supply host serial interface 0 conversion stages disabled 12345 678 91011012 910110 1 2 910110 1 second conversion sequence third conversion sequence 1 234 56 6 figure 44. recommended start-up sequence
AD7148 rev. 0 | page 33 of 56 typical application circuit 07155-044 AD7148 1 cin4 2 cin5 3 cin6 4 cin7 int 12 sclk 11 sda 10 ac shield 6 bias 7 gnd 8 v cc v drive cin3 16 cin2 15 cin1 14 cin0 13 int sck sdo host with i 2 c interface 2.2k ? 2.2k ? 2.2k ? slider button button button v drive v drive v drive v cc 2.7v to 3.6v 1 f to 10 f (optional) 0.1 f 10nf connect plane around sensors to ac shield 9 5 figure 45. typical application circuit
AD7148 rev. 0 | page 34 of 56 register map the AD7148 address space is divided into three different register banks, referred to as register bank 1, register bank 2, and register bank 3. figure 46 illustrates the division of these three banks. bank 1 registers contain control registers, cdc conversion control registers, interrupt enable registers, interrupt status registers, cdc 16-bit conversion data registers, device id registers, and proximity status registers. bank 2 registers contain the configuration registers used for uniquely configuring the cinx inputs for each conversion stage. initialize the bank 2 configuration registers immediately after power-up to obtain valid cdc conversion result data. bank 3 registers contain the results of each conversion stage. these registers automatically update at the end of each conversion sequence. although these registers are primarily used by the AD7148 internal data processing, they are accessible by the host processor for additional external data processing, if desired. default values are undefined for bank 2 registers and bank 3 registers until after power-up and configuration of the bank 2 registers. register ban k 1 addr 0x000 addr 0x018 addr 0x001 addr 0x005 addr 0x008 addr 0x00b addr 0x017 addr 0x013 addr 0x7f0 register ban k 2 addr 0x080 addr 0x0b8 addr 0x088 addr 0x090 addr 0x098 addr 0x0a0 addr 0x0a8 addr 0x0b0 register bank 3 addr 0x0e0 addr 0x1dc addr 0x104 addr 0x128 addr 0x14c addr 0x170 addr 0x194 addr 0x1b8 addr 0x042 addr 0x043 invalid do not access 24 registers proximity status register invalid do not access device id register cdc 16-bit conversion data (8 registers) interrupt status (3 registers) interrupt enable (3 registers) calibration and setup (4 registers) setup control (1 register) 64 registers 288 registers stage7 configuration (8 registers) stage6 configuration (8 registers) stage5 configuration (8 registers) stage4 configuration (8 registers) stage3 configuration (8 registers) stage2 configuration (8 registers) stage1 configuration (8 registers) stage0 configuration (8 registers) stage7 results (36 registers) stage6 results (36 registers) stage5 results (36 registers) stage4 results (36 registers) stage3 results (36 registers) stage2 results (36 registers) stage1 results (36 registers) stage0 results (36 registers) unused (4 registers) 07155-045 figure 46. layout of bank 1 registers, bank 2 registers, and bank 3 registers
AD7148 rev. 0 | page 35 of 56 detailed register descriptions bank 1 registers all addresses and default values are expressed in hexadecimal format. table 17. pwr_control register address data bit default value type mnemonic description 0x000 [1:0] 0 r/ w power_mode operating modes 00 = full power mode (normal operation, cdc conversions approximately every 36 ms) 01 = full shutdown mode (no cdc conversions) 10 = low power mode (automatic wake up operation) 11 = full shutdown mode (no cdc conversions) [3:2] 0 r/ w lp_conv_delay low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms [7:4] 0 r/ w sequence_stage_num number of stages in sequence (n + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence maximum value = 1011 = 12 conversion stages per sequence [9:8] 0 r/ w decimation adc decimation factor 00 = decimate by 256 01 = decimate by 128 10 = decimate by 64 11 = decimate by 64 [10] 0 r/ w sw_reset software reset control (self-clearing) 1 = resets all registers to default values [11] 0 r/ w int_pol interrupt polarity control 0 = active low 1 = active high [12] 0 r/ w excitation source control 0 = enable excitation source to cinx pins 1 = disable excitation source to cinx pins [13] 0 unused set to 0 [15:14] 0 r/ w cdc_bias cdc bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50%
AD7148 rev. 0 | page 36 of 56 table 18. stagex_cal_en register address data bit default value type mnemonic description 0x001 [0] 0 r/ w stage0_cal_en stage0 calibration enable 0 = disable 1 = enable [1] 0 r/ w stage1_cal_en stage1 calibration enable 0 = disable 1 = enable [2] 0 r/ w stage2_cal_en stage2 calibration enable 0 = disable 1 = enable [3] 0 r/ w stage3_cal_en stage3 calibration enable 0 = disable 1 = enable [4] 0 r/ w stage4_cal_en stage4 calibration enable 0 = disable 1 = enable [5] 0 r/ w stage5_cal_en stage5 calibration enable 0 = disable 1 = enable [6] 0 r/ w stage6_cal_en stage6 calibration enable 0 = disable 1 = enable [7] 0 r/ w stage7_cal_en stage7 calibration enable 0 = disable 1 = enable [11:8] 0 r/ w unused set unused register bits to 0 [13:12] 0 r/ w avg_fp_skip full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples [15:14] 0 r/ w avg_lp_skip low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples
AD7148 rev. 0 | page 37 of 56 table 19. amb_comp_ctrl0 register address data bit default value type mnemonic description 0x002 [3:0] 0 r/ w ff_skip_cnt fast filter skip control (n+1) 0000 = no sequence of results is skipped 0001 = one sequence of results is skipped for every one allowed into fast fifo 0010 = two sequences of results are skipped for every one allowed into fast fifo 1011 = maximum value = 8 sequences of results are skipped for every one allowed into fast fifo [7:4] f r/ w fp_proximity_cnt calibration disable period in full power mode = fp_proximity_cnt 16 time taken for one conversion sequence in full power mode [11:8] f r/ w lp_proximity_cnt calibration disable period in low power mode = lp_proximity_cnt 4 time taken for one conversion sequence in low power mode [13:12] 0 r/ w pwr_down_timeout full power to low power mode time out control 00 = 1.25 (fp_proximity_cnt) 01 = 1.50 (fp_proximity_cnt) 10 = 1.75 (fp_proximity_cnt) 11 = 2.00 (fp_proximity_cnt) [14] 0 r/ w forced_cal forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate [15] 0 r/ w conv_reset conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence back to stage0. table 20. amb_comp_ctrl1 register address data bit default value type mnemonic description 0x003 [7:0] 64 r/ w proximity_recal_lvl proximity recalibration level; value is multiplied by 16 to get actual recalibration level [13:8] 1 r/ w proximity_detection_rate proximity detection rate; value is multiplied by 16 to get actual detection rate [15:14] 0 r/ w slow_filter_update_lvl slow filter update level table 21. amb_comp_ctrl2 register address data bit default value type mnemonic description 0x004 [9:0] 3ff r/ w fp_proximity_recal full power mode proximity recalibration time control [15:10] 3f r/ w lp_proximity_recal low power mode proximity recalibration time control
AD7148 rev. 0 | page 38 of 56 table 22. stagex_low_int_en register address data bit default value type mnemonic description 0x005 [0] 0 r/ w stage0_low_int_en stage0 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [1] 0 r/ w stage1_low_int_en stage1 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage1 low threshold is exceeded [2] 0 r/ w stage2_low_int_en stage2 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage2 low threshold is exceeded [3] 0 r/ w stage3_low_int_en stage3 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage3 low threshold is exceeded [4] 0 r/ w stage4_low_int_en stage4 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage4 low threshold is exceeded [5] 0 r/ w stage5_low_int_en stage5 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage5 low threshold is exceeded [6] 0 r/ w stage6_low_int_en stage6 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage6 low threshold is exceeded [7] 0 r/ w stage7_low_int_en stage7 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage7 low threshold is exceeded [11:8] 0 unused set unused register bits to 0 [13:12] 0 r/ w gpio_setup gpio setup 00 = disable gpio pin 01 = configure gpio as an input 10 = configure gpio as an active low output 11 = configure gpio as an active high output [15:14] 0 r/ w gpio_input_config gpio input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level
AD7148 rev. 0 | page 39 of 56 table 23. stagex_high_int_en register address data bit default value type mnemonic description 0x006 [0] 0 r/ w stage0_high_int_en stage0 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [1] 0 r/ w stage1_high_int_en stage1 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage1 high threshold is exceeded [2] 0 r/ w stage2_high_int_en stage2 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage2 high threshold is exceeded [3] 0 r/ w stage3_high_int_en stage3 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage3 high threshold is exceeded [4] 0 r/ w stage4_high_int_en stage4 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage4 high threshold is exceeded [5] 0 r/ w stage5_high_int_en stage5 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage5 high threshold is exceeded [6] 0 r/ w stage6_high_int_en stage6 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage6 high threshold is exceeded [7] 0 r/ w stage7_high_int_en stage7 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage7 high threshold is exceeded [15:8] unused set unused register bits to 0
AD7148 rev. 0 | page 40 of 56 table 24. stagex_complete_int_en register address data bit default value type mnemonic description 0x007 [0] 0 r/ w stage0_complete_int_en stage0 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage0 conversion [1] 0 r/ w stage1_complete_int_en stage1 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage1 conversion [2] 0 r/ w stage2_complete_int_en stage2 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage2 conversion [3] 0 r/ w stage3_complete_int_en stage3 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage3 conversion [4] 0 r/ w stage4_complete_int_en stage4 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage4 conversion [5] 0 r/ w stage5_complete_int_en stage5 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage5 conversion [6] 0 r/ w stage6_complete_int_en stage6 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage6 conversion [7] 0 r/ w stage7_complete_int_en stage7 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage7 conversion [15:8] unused set unused register bits to 0 table 25. stagex_low_limit_int register 1 address data bit default value type mnemonic description 0x008 [0] 0 r stage0_low_limit_int stage0 cdc conversion low limit interrupt result 1 = indicates stage0_low_threshold value exceeded [1] 0 r stage1_low_limit_int stage1 cdc conversion low limit interrupt result 1 = indicates stage1_low_threshold value exceeded [2] 0 r stage2_low_limit_int stage2 cdc conversion low limit interrupt result 1 = indicates stage2_low_threshold value exceeded [3] 0 r stage3_low_limit_int stage3 cdc conversion low limit interrupt result 1 = indicates stage3_low_threshold value exceeded [4] 0 r stage4_low_limit_int stage4 cdc conversion low limit interrupt result 1 = indicates stage4_low_threshold value exceeded [5] 0 r stage5_low_limit_int stage5 cdc conversion low limit interrupt result 1 = indicates stage5_low_threshold value exceeded [6] 0 r stage6_low_limit_int stage6 cdc conversion low limit interrupt result 1 = indicates stage6_low_threshold value exceeded [7] 0 r stage7_low_limit_int stage7 cdc conversion low limit interrupt result 1 = indicates stage7_low_threshold value exceeded [15:8] unused set unused register bits to 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded.
AD7148 rev. 0 | page 41 of 56 table 26. stagex_high_limit_int register 1 address data bit default value type mnemonic description 0x009 [0] 0 r stage0_high_limit_int stage0 cdc conversion high limit interrupt result 1 = indicates stage0_high_threshold value exceeded [1] 0 r stage1_high_limit_int stage1 cdc conversion high limit interrupt result 1 = indicates stage1_high_threshold value exceeded [2] 0 r stage2_high_limit_int stage2 cdc conversion high limit interrupt result 1 = indicates stage2_high_threshold value exceeded [3] 0 r stage3_high_limit_int stage3 cdc conversion high limit interrupt result 1 = indicates stage3_high_threshold value exceeded [4] 0 r stage4_high_limit_int stage4 cdc conversion high limit interrupt result 1 = indicates stage4_high_threshold value exceeded [5] 0 r stage5_high_limit_int stage5 cdc conversion high limit interrupt result 1 = indicates stage5_high_threshold value exceeded [6] 0 r stage6_high_limit_int stage6 cdc conversion high limit interrupt result 1 = indicates stage6_high_threshold value exceeded [7] 0 r stage7_high_limit_int stage7 cdc conversion high limit interrupt result 1 = indicates stage7_high_threshold value exceeded [15:8] unused set unused register bits to 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded. table 27. stagex_complete_int_status register 1 address data bit default value type mnemonic description 0x00a [0] 0 r stage0_complete_int_status stage0 conversion complete register interrupt status 1 = indicates stage0 conversion completed [1] 0 r stage1_complete_int_status stage1 conversion complete register interrupt status 1 = indicates stage1 conversion completed [2] 0 r stage2_complete_int_status stage2 conversion complete register interrupt status 1 = indicates stage2 conversion completed [3] 0 r stage3_complete_int_status stage3 conversion complete register interrupt status 1 = indicates stage3 conversion completed [4] 0 r stage4_complete_int_status stage4 conversion complete register interrupt status 1 = indicates stage4 conversion completed [5] 0 r stage5_complete_int_status stage5 conversion complete register interrupt status 1 = indicates stage5 conversion completed [6] 0 r stage6_complete_int_status stage6 conversion complete register interrupt status 1 = indicates stage6 conversion completed [7] 0 r stage7_complete_int_status stage7 conversion complete register interrupt status 1 = indicates stage7 conversion completed [15:8] unused set unused register bits to 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded.
AD7148 rev. 0 | page 42 of 56 table 28. cdc 16-bit conversion data registers address data bit default value type mnemonic description 0x00b [15:0] 0 r cdc_result_s0 stage0 cdc 16-bit conversion data 0x00c [15:0] 0 r cdc_result_s1 stage1 cdc 16-bit conversion data 0x00d [15:0] 0 r cdc_result_s2 stage2 cdc 16-bit conversion data 0x00e [15:0] 0 r cdc_result_s3 stage3 cdc 16-bit conversion data 0x00f [15:0] 0 r cdc_result_s4 stage4 cdc 16-bit conversion data 0x010 [15:0] 0 r cdc_result_s5 stage5 cdc 16-bit conversion data 0x011 [15:0] 0 r cdc_result_s6 stage6 cdc 16-bit conversion data 0x012 [15:0] 0 r cdc_result_s7 stage7 cdc 16-bit conversion data table 29. device id register address data bit default value type mnemonic description 0x017 [3:0] 0 r revision_code AD7148 revision code [15:4] 148 r devid AD7148 device id = 0x148 table 30. proximity status register address data bit default value type mnemonic description 0x042 [0] 0 r stage0_proximity_status stage0 proximity status register 1 = indicates proximity has been detected on stage0 [1] 0 r stage1_proximity_status stage1 proximity status register 1 = indicates proximity has been detected on stage1 [2] 0 r stage2_proximity_status stage2 proximity status register 1 = indicates proximity has been detected on stage2 [3] 0 r stage3_proximity_status stage3 proximity status register 1 = indicates proximity has been detected on stage3 [4] 0 r stage4_proximity_status stage4 proximity status register 1 = indicates proximity has been detected on stage4 [5] 0 r stage5_proximity_status stage5 proximity status register 1 = indicates proximity has been detected on stage5 [6] 0 r stage6_proximity_status stage6 proximity status register 1 = indicates proximity has been detected on stage6 [7] 0 r stage7_proximity_status stage7 proximity status register 1 = indicates proximity has been detected on stage7 [15:8] unused set unused register bits to 0
AD7148 rev. 0 | page 43 of 56 bank 2 registers all address values are expressed in hexadecimal format. table 31. stage0 configuration registers address data bit default value type mnemonic description 0x080 [15:0] x r/ w stage0_connection_setup[6:0] stage0 cin[6:0] connection setup (see table 39 ) 0x081 [15:0] x r/ w stage0_connection_setup[7] stage0 cin7 connection setup (see table 40 ) 0x082 [15:0] x r/ w stage0_afe_offset stage0 afe offset control (see table 41 ) 0x083 [15:0] x r/ w stage0_sensitivity stage0 sensitivity control (see table 42 ) 0x084 [15:0] x r/ w stage0_offset_low stage0 initial offset low value 0x085 [15:0] x r/ w stage0_offset_high stage0 initial offset high value 0x086 [15:0] x r/ w stage0_offset_high_clamp stage0 offset high clamp value 0x087 [15:0] x r/ w stage0_ offset_low_clamp stage0 offset low clamp value table 32. stage1 configuration registers address data bit default value type mnemonic description 0x088 [15:0] x r/ w stage1_connection_setup[6:0] stage1 cin[6:0] connection setup (see table 39 ) 0x089 [15:0] x r/ w stage1_connection_setup[7] stage1 cin7 connection setup (see table 40 ) 0x08a [15:0] x r/ w stage1_afe_offset stage1 afe offset control (see table 41 ) 0x08b [15:0] x r/ w stage1_sensitivity stage1 sensitivity control (see table 42 ) 0x08c [15:0] x r/ w stage1_offset_low stage1 initial offset low value 0x08d [15:0] x r/ w stage1_offset_high stage1 initial offset high value 0x08e [15:0] x r/ w stage1_offset_high_clamp stage1 offset high clamp value 0x08f [15:0] x r/ w stage1_offset_low_clamp stage1 offset low clamp value table 33. stage2 configuration registers address data bit default value type mnemonic description 0x090 [15:0] x r/ w stage2_connection_setup[6:0] stage2 cin[6:0] connection setup (see table 39 ) 0x091 [15:0] x r/ w stage2_connection_setup[7] stage2 cin7 connection setup (see table 40 ) 0x092 [15:0] x r/ w stage2_afe_offset stage2 afe offset control (see table 41 ) 0x093 [15:0] x r/ w stage2_sensitivity stage2 sensitivity control (see table 42 ) 0x094 [15:0] x r/ w stage2_offset_low stage2 initial offset low value 0x095 [15:0] x r/ w stage2_offset_high stage2 initial offset high value 0x096 [15:0] x r/ w stage2_offset_high_clamp stage2 offset high clamp value 0x097 [15:0] x r/ w stage2_offset_low_clamp stage2 offset low clamp value
AD7148 rev. 0 | page 44 of 56 table 34. stage3 configuration registers address data bit default value type mnemonic description 0x098 [15:0] x r/ w stage3_connection_setup[6:0] stage3 cin[6:0] connection setup (see table 39 ) 0x099 [15:0] x r/ w stage3_connection_setup[7] stage3 cin7 connection setup (see table 40 ) 0x09a [15:0] x r/ w stage3_afe_offset stage3 afe offset control (see table 41 ) 0x09b [15:0] x r/ w stage3_sensitivity stage3 sensitivity control (see table 42 ) 0x09c [15:0] x r/ w stage3_offset_low stage3 initial offset low value 0x09d [15:0] x r/ w stage3_offset_high stage3 initial offset high value 0x09e [15:0] x r/ w stage3_offset_high_clamp stage3 offset high clamp value 0x09f [15:0] x r/ w stage3_offset_low_clamp stage3 offset low clamp value table 35. stage4 configuration registers address data bit default value type mnemonic description 0x0a0 [15:0] x r/ w stage4_connection_setup[6:0] stage4 cin[6:0] connection setup (see table 39 ) 0x0a1 [15:0] x r/ w stage4_connection_setup[7] stage4 cin7 connection setup (see table 40 ) 0x0a2 [15:0] x r/ w stage4_afe_offset stage4 afe offset control (see table 41 ) 0x0a3 [15:0] x r/ w stage4_sensitivity stage4 sensitivity control (see table 42 ) 0x0a4 [15:0] x r/ w stage4_offset_low stage4 initial offset low value 0x0a5 [15:0] x r/ w stage4_offset_high stage4 initial offset high value 0x0a6 [15:0] x r/ w stage4_offset_high_clamp stage4 offset high clamp value 0x0a7 [15:0] x r/ w stage4_offset_low_clamp stage4 offset low clamp value table 36. stage5 configuration registers address data bit default value type name description 0x0a8 [15:0] x r/ w stage5_connection_setup[6:0] stage5 cin[6:0] connection setup (see table 39 ) 0x0a9 [15:0] x r/ w stage5_connection_setup[7] stage5 cin7 connection setup (see table 40 ) 0x0aa [15:0] x r/ w stage5_afe_offset stage5 afe offset control (see table 41 ) 0x0ab [15:0] x r/ w stage5_sensitivity stage5 sensitivity control (see table 42 ) 0x0ac [15:0] x r/ w stage5_offset_low stage5 initial offset low value 0x0ad [15:0] x r/ w stage5_offset_high stage5 initial offset high value 0x0ae [15:0] x r/ w stage5_offset_high_clamp stage5 offset high clamp value 0x0af [15:0] x r/ w stage5_offset_low_clamp stage5 offset low clamp value table 37. stage6 configuration registers address data bit default value type mnemonic description 0x0b0 [15:0] x r/ w stage6_connection_setup[6:0] stage6 cin[6:0] connection setup (see table 39 ) 0x0b1 [15:0] x r/ w stage6_connection_setup[7] stage6 cin7 connection setup (see table 40 ) 0x0b2 [15:0] x r/ w stage6_afe_offset stage6 afe offset control (see table 41 ) 0x0b3 [15:0] x r/ w stage6_sensitivity stage6 sensitivity control (see table 42 ) 0x0b4 [15:0] x r/ w stage6_offset_low stage6 initial offset low value 0x0b5 [15:0] x r/ w stage6_offset_high stage6 initial offset high value 0x0b6 [15:0] x r/ w stage6_offset_high_clamp stage6 offset high clamp value 0x0b7 [15:0] x r/ w stage6_offset_low_clamp stage6 offset low clamp value
AD7148 rev. 0 | page 45 of 56 table 38. stage7 configuration registers address data bit default value type mnemonic description 0x0b8 [15:0] x r/ w stage7_connection_setup[6:0] stage7 cin[6:0] connection setup (see table 39 ) 0x0b9 [15:0] x r/ w stage7_connection_setup[7] stage7 cin7 connection setup (see table 40 ) 0x0ba [15:0] x r/ w stage7_afe_offset stage7 afe offset control (see table 41 ) 0x0bb [15:0] x r/ w stage7_sensitivity stage7 sensitivity control (see table 42 ) 0x0bc [15:0] x r/ w stage7_offset_low stage7 initial offset low value 0x0bd [15:0] x r/ w stage7_offset_high stage7 initial offset high value 0x0be [15:0] x r/ w stage7_offset_high_clamp stage7 offset high clamp value 0x0bf [15:0] x r/ w stage7_offset_low_clamp stage7 offset low clamp value table 39. stagex detailed cin[0:6] conn ection setup description (x = 0 to 7) data bit default value type mnemonic description [1:0] x r/ w cin0_connection_setup cin0 connection setup 00 = cin0 not connected to cdc inputs 01 = cin0 connected to cdc negative input 10 = cin0 connected to cdc positive input 11 = cin0 connected to bias (connect unused cinx inputs) [3:2] x r/ w cin1_connection_setup cin1 connection setup 00 = cin1 not connected to cdc inputs 01 = cin1 connected to cdc negative input 10 = cin1 connected to cdc positive input 11 = cin1 connected to bias (connect unused cinx inputs) [5:4] x r/ w cin2_connection_setup cin2 connection setup 00 = cin2 not connected to cdc inputs 01 = cin2 connected to cdc negative input 10 = cin2 connected to cdc positive input 11 = cin2 connected to bias (connect unused cinx inputs) [7:6] x r/ w cin3_connection_setup cin3 connection setup 00 = cin3 not connected to cdc inputs 01 = cin3 connected to cdc negative input 10 = cin3 connected to cdc positive input 11 = cin3 connected to bias (connect unused cinx inputs) [9:8] x r/ w cin4_connection_setup cin4 connection setup 00 = cin4 not connected to cdc inputs 01 = cin4 connected to cdc negative input 10 = cin4 connected to cdc positive input 11 = cin4 connected to bias (connect unused cinx inputs) [11:10] x r/ w cin5_connection_setup cin5 connection setup 00 = cin5 not connected to cdc inputs 01 = cin5 connected to cdc negative input 10 = cin5 connected to cdc positive input 11 = cin5 connected to bias (connect unused cinx inputs) [13:12] x r/ w cin6_connection_setup cin6 connection setup 00 = cin6 not connected to cdc inputs 01 = cin6 connected to cdc negative input 10 = cin6 connected to cdc positive input 11 = cin6 connected to bias (connect unused cinx inputs) [15:14] x unused set unused register bits to 0
AD7148 rev. 0 | page 46 of 56 table 40. stagex detailed cin7 connec tion setup description (x = 0 to 7) data bit default value type mnemonic description [1:0] x r/ w cin7_connection_setup cin7 connection setup 00 = cin7 not connected to cdc inputs 01 = cin7 connected to cdc negative input 10 = cin7 connected to cdc positive input 11 = cin7 connected to bias (connect unused cinx inputs) [12:2] x unused set unused register bits to 0 [13:12] x r/ w se_connection_setup single-ended measurement connection setup 00 = do not use 01 = use when one cin is connected to cdc positive input, single-ended measurements only 10 = use when one cin is connected to cdc negative input, single-ended measurements only 11 = differential connection to cdc [14] x r/ w neg_afe_offset_disable negative afe offset enable control 0 = enable 1 = disable [15] x r/ w pos_afe_offset_disable positive afe offset enable control 0 = enable 1 = disable table 41. stagex detailed offset control description (x = 0 to 7) data bit default value type mnemonic description [5:0] x r/ w neg_afe_offset negative afe offset setting (20 pf range) 1 lsb value = 0.32 pf of offset [6] x unused set to 0 [7] x r/ w neg_afe_offset_swap negative afe offset swap control 0 = neg_afe_offset applied to cdc negative input 1 = neg_afe_offset applied to cdc positive input [13:8] x r/ w pos_afe_offset positive afe offset setting (20 pf range) 1 lsb value = 0.32 pf of offset [14] x unused set to 0 [15] x r/ w pos_afe_offset_swap positive afe offset swap control 0 = pos_afe_offset applied to cdc positive input 1 = pos_afe_offset applied to cdc negative input
AD7148 rev. 0 | page 47 of 56 table 42. stagex detailed sensitivity control description (x = 0 to 7) data bit default value type mnemonic description [3:0] x r/ w neg_threshold_sensitivity negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.48%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [6:4] x r/ w neg_peak_detect negative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [7] x unused set to 0 [11:8] x r/ w pos_threshold_sensitivity positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.48%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [14:12] x r/ w pos_peak_detect positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [15] x unused set to 0
AD7148 rev. 0 | page 48 of 56 bank 3 registers all address values are expressed in hexadecimal format. table 43. stage0 results registers address data bit default value type mnemonic description 0x0e0 [15:0] x r/ w stage0_conv_data stage0 cdc 16-bit conversion data (copy of data in cdc_result_s0 register) 0x0e1 [15:0] x r/ w stage0_ff_word0 stage0 fast fifo word0 0x0e2 [15:0] x r/ w stage0_ff_word1 stage0 fast fifo word1 0x0e3 [15:0] x r/ w stage0_ff_word2 stage0 fast fifo word2 0x0e4 [15:0] x r/ w stage0_ff_word3 stage0 fast fifo word3 0x0e5 [15:0] x r/ w stage0_ff_word4 stage0 fast fifo word4 0x0e6 [15:0] x r/ w stage0_ff_word5 stage0 fast fifo word5 0x0e7 [15:0] x r/ w stage0_ff_word6 stage0 fast fifo word6 0x0e8 [15:0] x r/ w stage0_ff_word7 stage0 fast fifo word7 0x0e9 [15:0] x r/ w stage0_sf_word0 stage0 slow fifo word0 0x0ea [15:0] x r/ w stage0_sf_word1 stage0 slow fifo word1 0x0eb [15:0] x r/ w stage0_sf_word2 stage0 slow fifo word2 0x0ec [15:0] x r/ w stage0_sf_word3 stage0 slow fifo word3 0x0ed [15:0] x r/ w stage0_sf_word4 stage0 slow fifo word4 0x0ee [15:0] x r/ w stage0_sf_word5 stage0 slow fifo word5 0x0ef [15:0] x r/ w stage0_sf_word6 stage0 slow fifo word6 0x0f0 [15:0] x r/ w stage0_sf_word7 stage0 slow fifo word7 0x0f1 [15:0] x r/ w stage0_sf_ambient stage0 slow fifo ambient value 0x0f2 [15:0] x r/ w stage0_ff_avg stage0 fast fifo average value 0x0f3 [15:0] x r/ w stage0_peak_detect_word0 stage0 peak fifo word0 value 0x0f4 [15:0] x r/ w stage0_peak_detect_word1 stage0 peak fifo word1 value 0x0f5 [15:0] x r/ w stage0_max_word0 stage0 maximum value fifo word0 0x0f6 [15:0] x r/ w stage0_max_word1 stage0 maximum value fifo word1 0x0f7 [15:0] x r/ w stage0_max_word2 stage0 maximum value fifo word2 0x0f8 [15:0] x r/ w stage0_max_word3 stage0 maximum value fifo word3 0x0f9 [15:0] x r/ w stage0_max_avg stage0 average maximum fifo value 0x0fa [15:0] x r/ w stage0_high_threshold stage0 high threshold value 0x0fb [15:0] x r/ w stage0_max_temp stage0 temporary maximum value 0x0fc [15:0] x r/ w stage0_min_word0 stage0 minimum value fifo word0 0x0fd [15:0] x r/ w stage0_min_word1 stage0 minimum value fifo word1 0x0fe [15:0] x r/ w stage0_min_word2 stage0 minimum value fifo word2 0x0ff [15:0] x r/ w stage0_min_word3 stage0 minimum value fifo word3 0x100 [15:0] x r/ w stage0_min_avg stage0 average minimum fifo value 0x101 [15:0] x r/ w stage0_low_threshold stage0 low threshold value 0x102 [15:0] x r/ w stage0_min_temp stage0 temporary minimum value 0x103 [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 49 of 56 table 44. stage1 results registers address data bit default value type mnemonic description 0x104 [15:0] x r/ w stage1_conv_data stage1 cdc 16-bit conversion data (copy of data in cdc_result_s1 register) 0x105 [15:0] x r/ w stage1_ff_word0 stage1 fast fifo word0 0x106 [15:0] x r/ w stage1_ff_word1 stage1 fast fifo word1 0x107 [15:0] x r/ w stage1_ff_word2 stage1 fast fifo word2 0x108 [15:0] x r/ w stage1_ff_word3 stage1 fast fifo word3 0x109 [15:0] x r/ w stage1_ff_word4 stage1 fast fifo word4 0x10a [15:0] x r/ w stage1_ff_word5 stage1 fast fifo word5 0x10b [15:0] x r/ w stage1_ff_word6 stage1 fast fifo word6 0x10c [15:0] x r/ w stage1_ff_word7 stage1 fast fifo word7 0x10d [15:0] x r/ w stage1_sf_word0 stage1 slow fifo word0 0x10e [15:0] x r/ w stage1_sf_word1 stage1 slow fifo word1 0x10f [15:0] x r/ w stage1_sf_word2 stage1 slow fifo word2 0x110 [15:0] x r/ w stage1_sf_word3 stage1 slow fifo word3 0x111 [15:0] x r/ w stage1_sf_word4 stage1 slow fifo word4 0x112 [15:0] x r/ w stage1_sf_word5 stage1 slow fifo word5 0x113 [15:0] x r/ w stage1_sf_word6 stage1 slow fifo word6 0x114 [15:0] x r/ w stage1_sf_word7 stage1 slow fifo word7 0x115 [15:0] x r/ w stage1_sf_ambient stage1 slow fifo ambient value 0x116 [15:0] x r/ w stage1_ff_avg stage1 fast fifo average value 0x117 [15:0] x r/ w stage1_cdc_word0 stage1 cdc fifo word0 0x118 [15:0] x r/ w stage1_cdc_word1 stage1 cdc fifo word1 0x119 [15:0] x r/ w stage1_max_word0 stage1 maximum value fifo word0 0x11a [15:0] x r/ w stage1_max_word1 stage1 maximum value fifo word1 0x11b [15:0] x r/ w stage1_max_word2 stage1 maximum value fifo word2 0x11c [15:0] x r/ w stage1_max_word3 stage1 maximum value fifo word3 0x11d [15:0] x r/ w stage1_max_avg stage1 average maximum fifo value 0x11e [15:0] x r/ w stage1_high_threshold stage1 high threshold value 0x11f [15:0] x r/ w stage1_max_temp stage1 temporary maximum value 0x120 [15:0] x r/ w stage1_min_word0 stage1 minimum value fifo word0 0x121 [15:0] x r/ w stage1_min_word1 stage1 minimum value fifo word1 0x122 [15:0] x r/ w stage1_min_word2 stage1 minimum value fifo word2 0x123 [15:0] x r/ w stage1_min_word3 stage1 minimum value fifo word3 0x124 [15:0] x r/ w stage1_min_avg stage1 average minimum fifo value 0x125 [15:0] x r/ w stage1_low_threshold stage1 low threshold value 0x126 [15:0] x r/ w stage1_min_temp stage1 temporary minimum value 0x127 [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 50 of 56 table 45. stage2 results registers address data bit default value type mnemonic description 0x128 [15:0] x r/ w stage2_conv_data stage2 cdc 16-bit conversion data (copy of data in cdc_result_s2 register) 0x129 [15:0] x r/ w stage2_ff_word0 stage2 fast fifo word0 0x12a [15:0] x r/ w stage2_ff_word1 stage2 fast fifo word1 0x12b [15:0] x r/ w stage2_ff_word2 stage2 fast fifo word2 0x12c [15:0] x r/ w stage2_ff_word3 stage2 fast fifo word3 0x12d [15:0] x r/ w stage2_ff_word4 stage2 fast fifo word4 0x12e [15:0] x r/ w stage2_ff_word5 stage2 fast fifo word5 0x12f [15:0] x r/ w stage2_ff_word6 stage2 fast fifo word6 0x130 [15:0] x r/ w stage2_ff_word7 stage2 fast fifo word7 0x131 [15:0] x r/ w stage2_sf_word0 stage2 slow fifo word0 0x132 [15:0] x r/ w stage2_sf_word1 stage2 slow fifo word1 0x133 [15:0] x r/ w stage2_sf_word2 stage2 slow fifo word2 0x134 [15:0] x r/ w stage2_sf_word3 stage2 slow fifo word3 0x135 [15:0] x r/ w stage2_sf_word4 stage2 slow fifo word4 0x136 [15:0] x r/ w stage2_sf_word5 stage2 slow fifo word5 0x137 [15:0] x r/ w stage2_sf_word6 stage2 slow fifo word6 0x138 [15:0] x r/ w stage2_sf_word7 stage2 slow fifo word7 0x139 [15:0] x r/ w stage2_sf_ambient stage2 slow fifo ambient value 0x13a [15:0] x r/ w stage2_ff_avg stage2 fast fifo average value 0x13b [15:0] x r/ w stage2_cdc_word0 stage2 cdc fifo word0 0x13c [15:0] x r/ w stage2_cdc_word1 stage2 cdc fifo word1 0x13d [15:0] x r/ w stage2_max_word0 stage2 maximum value fifo word0 0x13e [15:0] x r/ w stage2_max_word1 stage2 maximum value fifo word1 0x13f [15:0] x r/ w stage2_max_word2 stage2 maximum value fifo word2 0x140 [15:0] x r/ w stage2_max_word3 stage2 maximum value fifo word3 0x141 [15:0] x r/ w stage2_max_avg stage2 average maximum fifo value 0x142 [15:0] x r/ w stage2_high_threshold stage2 high threshold value 0x143 [15:0] x r/ w stage2_max_temp stage2 temporary maximum value 0x144 [15:0] x r/ w stage2_min_word0 stage2 minimum value fifo word0 0x145 [15:0] x r/ w stage2_min_word1 stage2 minimum value fifo word1 0x146 [15:0] x r/ w stage2_min_word2 stage2 minimum value fifo word2 0x148 [15:0] x r/ w stage2_min_word3 stage2 minimum value fifo word3 0x148 [15:0] x r/ w stage2_min_avg stage2 average minimum fifo value 0x149 [15:0] x r/ w stage2_low_threshold stage2 low threshold value 0x14a [15:0] x r/ w stage2_min_temp stage2 temporary minimum value 0x14b [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 51 of 56 table 46. stage3 results registers address data bit default value type mnemonic description 0x14c [15:0] x r/ w stage3_conv_data stage3 cdc 16-bit conversion data (copy of data in cdc_result_s3 register) 0x14d [15:0] x r/ w stage3_ff_word0 stage3 fast fifo word0 0x14e [15:0] x r/ w stage3_ff_word1 stage3 fast fifo word1 0x14f [15:0] x r/ w stage3_ff_word2 stage3 fast fifo word2 0x150 [15:0] x r/ w stage3_ff_word3 stage3 fast fifo word3 0x151 [15:0] x r/ w stage3_ff_word4 stage3 fast fifo word4 0x152 [15:0] x r/ w stage3_ff_word5 stage3 fast fifo word5 0x153 [15:0] x r/ w stage3_ff_word6 stage3 fast fifo word6 0x154 [15:0] x r/ w stage3_ff_word7 stage3 fast fifo word7 0x155 [15:0] x r/ w stage3_sf_word0 stage3 slow fifo word0 0x156 [15:0] x r/ w stage3_sf_word1 stage3 slow fifo word1 0x157 [15:0] x r/ w stage3_sf_word2 stage3 slow fifo word2 0x158 [15:0] x r/ w stage3_sf_word3 stage3 slow fifo word3 0x159 [15:0] x r/ w stage3_sf_word4 stage3 slow fifo word4 0x15a [15:0] x r/ w stage3_sf_word5 stage3 slow fifo word5 0x15b [15:0] x r/ w stage3_sf_word6 stage3 slow fifo word6 0x15c [15:0] x r/ w stage3_sf_word7 stage3 slow fifo word7 0x15d [15:0] x r/ w stage3_sf_ambient stage3 slow fifo ambient value 0x15e [15:0] x r/ w stage3_ff_avg stage3 fast fifo average value 0x15f [15:0] x r/ w stage3_cdc_word0 stage3 cdc fifo word0 0x160 [15:0] x r/ w stage3_cdc_word1 stage3 cdc fifo word1 0x161 [15:0] x r/ w stage3_max_word0 stage3 maximum value fifo word0 0x162 [15:0] x r/ w stage3_max_word1 stage3 maximum value fifo word1 0x163 [15:0] x r/ w stage3_max_word2 stage3 maximum value fifo word2 0x164 [15:0] x r/ w stage3_max_word3 stage3 maximum value fifo word3 0x165 [15:0] x r/ w stage3_max_avg stage3 average maximum fifo value 0x166 [15:0] x r/ w stage3_high_threshold stage3 high threshold value 0x167 [15:0] x r/ w stage3_max_temp stage3 temporary maximum value 0x168 [15:0] x r/ w stage3_min_word0 stage3 minimum value fifo word0 0x169 [15:0] x r/ w stage3_min_word1 stage3 minimum value fifo word1 0x16a [15:0] x r/ w stage3_min_word2 stage3 minimum value fifo word2 0x16b [15:0] x r/ w stage3_min_word3 stage3 minimum value fifo word3 0x16c [15:0] x r/ w stage3_min_avg stage3 average minimum fifo value 0x16d [15:0] x r/ w stage3_low_threshold stage3 low threshold value 0x16e [15:0] x r/ w stage3_min_temp stage3 temporary minimum value 0x16f [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 52 of 56 table 47. stage4 results registers address data bit default value type mnemonic description 0x170 [15:0] x r/ w stage4_conv_data stage4 cdc 16-bit conversion data (copy of data in cdc_result_s4 register) 0x171 [15:0] x r/ w stage4_ff_word0 stage4 fast fifo word0 0x172 [15:0] x r/ w stage4_ff_word1 stage4 fast fifo word1 0x173 [15:0] x r/ w stage4_ff_word2 stage4 fast fifo word2 0x174 [15:0] x r/ w stage4_ff_word3 stage4 fast fifo word3 0x175 [15:0] x r/ w stage4_ff_word4 stage4 fast fifo word4 0x176 [15:0] x r/ w stage4_ff_word5 stage4 fast fifo word5 0x177 [15:0] x r/ w stage4_ff_word6 stage4 fast fifo word6 0x178 [15:0] x r/ w stage4_ff_word7 stage4 fast fifo word7 0x179 [15:0] x r/ w stage4_sf_word0 stage4 slow fifo word0 0x17a [15:0] x r/ w stage4_sf_word1 stage4 slow fifo word1 0x17b [15:0] x r/ w stage4_sf_word2 stage4 slow fifo word2 0x17c [15:0] x r/ w stage4_sf_word3 stage4 slow fifo word3 0x17d [15:0] x r/ w stage4_sf_word4 stage4 slow fifo word4 0x17e [15:0] x r/ w stage4_sf_word5 stage4 slow fifo word5 0x17f [15:0] x r/ w stage4_sf_word6 stage4 slow fifo word6 0x180 [15:0] x r/ w stage4_sf_word7 stage4 slow fifo word7 0x181 [15:0] x r/ w stage4_sf_ambient stage4 slow fifo ambient value 0x182 [15:0] x r/ w stage4_ff_avg stage4 fast fifo average value 0x183 [15:0] x r/ w stage4_cdc_word0 stage4 cdc fifo word0 0x184 [15:0] x r/ w stage4_cdc_word1 stage4 cdc fifo word1 0x185 [15:0] x r/ w stage4_max_word0 stage4 maximum value fifo word0 0x186 [15:0] x r/ w stage4_max_word1 stage4 maximum value fifo word1 0x187 [15:0] x r/ w stage4_max_word2 stage4 maximum value fifo word2 0x188 [15:0] x r/ w stage4_max_word3 stage4 maximum value fifo word3 0x189 [15:0] x r/ w stage4_max_avg stage4 average maximum fifo value 0x18a [15:0] x r/ w stage4_high_threshold stage4 high threshold value 0x18b [15:0] x r/ w stage4_max_temp stage4 temporary maximum value 0x18c [15:0] x r/ w stage4_min_word0 stage4 minimum value fifo word0 0x18d [15:0] x r/ w stage4_min_word1 stage4 minimum value fifo word1 0x18e [15:0] x r/ w stage4_min_word2 stage4 minimum value fifo word2 0x18f [15:0] x r/ w stage4_min_word3 stage4 minimum value fifo word3 0x190 [15:0] x r/ w stage4_min_avg stage4 average minimum fifo value 0x191 [15:0] x r/ w stage4_low_threshold stage4 low threshold value 0x192 [15:0] x r/ w stage4_min_temp stage4 temporary minimum value 0x193 [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 53 of 56 table 48. stage5 results registers address data bit default value type mnemonic description 0x194 [15:0] x r/ w stage5_conv_data stage5 cdc 16-bit conversion data (copy of data in cdc_result_s5 register) 0x195 [15:0] x r/ w stage5_ff_word0 stage5 fast fifo word0 0x196 [15:0] x r/ w stage5_ff_word1 stage5 fast fifo word1 0x197 [15:0] x r/ w stage5_ff_word2 stage5 fast fifo word2 0x198 [15:0] x r/ w stage5_ff_word3 stage5 fast fifo word3 0x199 [15:0] x r/ w stage5_ff_word4 stage5 fast fifo word4 0x19a [15:0] x r/ w stage5_ff_word5 stage5 fast fifo word5 0x19b [15:0] x r/ w stage5_ff_word6 stage5 fast fifo word6 0x19c [15:0] x r/ w stage5_ff_word7 stage5 fast fifo word7 0x19d [15:0] x r/ w stage5_sf_word0 stage5 slow fifo word0 0x19e [15:0] x r/ w stage5_sf_word1 stage5 slow fifo word1 0x19f [15:0] x r/ w stage5_sf_word2 stage5 slow fifo word2 0x1a0 [15:0] x r/ w stage5_sf_word3 stage5 slow fifo word3 0x1a1 [15:0] x r/ w stage5_sf_word4 stage5 slow fifo word4 0x1a2 [15:0] x r/ w stage5_sf_word5 stage5 slow fifo word5 0x1a3 [15:0] x r/ w stage5_sf_word6 stage5 slow fifo word6 0x1a4 [15:0] x r/ w stage5_sf_word7 stage5 slow fifo word7 0x1a5 [15:0] x r/ w stage5_sf_ambient stage5 slow fifo ambient value 0x1a6 [15:0] x r/ w stage5_ff_avg stage5 fast fifo average value 0x1a7 [15:0] x r/ w stage5_cdc_word0 stage5 cdc fifo word0 0x1a8 [15:0] x r/ w stage5_cdc_word1 stage5 cdc fifo word1 0x1a9 [15:0] x r/ w stage5_max_word0 stage5 maximum value fifo word0 0x1aa [15:0] x r/ w stage5_max_word1 stage5 maximum value fifo word1 0x1ab [15:0] x r/ w stage5_max_word2 stage5 maximum value fifo word2 0x1ac [15:0] x r/ w stage5_max_word3 stage5 maximum value fifo word3 0x1ad [15:0] x r/ w stage5_max_avg stage5 average maximum fifo value 0x1ae [15:0] x r/ w stage5_high_threshold stage5 high threshold value 0x1af [15:0] x r/ w stage5_max_temp stage5 temporary maximum value 0x1b0 [15:0] x r/ w stage5_min_word0 stage5 minimum value fifo word0 0x1b1 [15:0] x r/ w stage5_min_word1 stage5 minimum value fifo word1 0x1b2 [15:0] x r/ w stage5_min_word2 stage5 minimum value fifo word2 0x1b3 [15:0] x r/ w stage5_min_word3 stage5 minimum value fifo word3 0x1b4 [15:0] x r/ w stage5_min_avg stage5 average minimum fifo value 0x1b5 [15:0] x r/ w stage5_low_threshold stage5 low threshold value 0x1b6 [15:0] x r/ w stage5_min_temp stage5 temporary minimum value 0x1b7 [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 54 of 56 table 49. stage6 results registers address data bit default value type mnemonic description 0x1b8 [15:0] x r/ w stage6_conv_data stage6 cdc 16-bit conversion data (copy of data in cdc_result_s6 register) 0x1b9 [15:0] x r/ w stage6_ff_word0 stage6 fast fifo word0 0x1ba [15:0] x r/ w stage6_ff_word1 stage6 fast fifo word1 0x1bb [15:0] x r/ w stage6_ff_word2 stage6 fast fifo word2 0x1bc [15:0] x r/ w stage6_ff_word3 stage6 fast fifo word3 0x1bd [15:0] x r/ w stage6_ff_word4 stage6 fast fifo word4 0x1be [15:0] x r/ w stage6_ff_word5 stage6 fast fifo word5 0x1bf [15:0] x r/ w stage6_ff_word6 stage6 fast fifo word6 0x1c0 [15:0] x r/ w stage6_ff_word7 stage6 fast fifo word7 0x1c1 [15:0] x r/ w stage6_sf_word0 stage6 slow fifo word0 0x1c2 [15:0] x r/ w stage6_sf_word1 stage6 slow fifo word1 0x1c3 [15:0] x r/ w stage6_sf_word2 stage6 slow fifo word2 0x1c4 [15:0] x r/ w stage6_sf_word3 stage6 slow fifo word3 0x1c5 [15:0] x r/ w stage6_sf_word4 stage6 slow fifo word4 0x1c6 [15:0] x r/ w stage6_sf_word5 stage6 slow fifo word5 0x1c7 [15:0] x r/ w stage6_sf_word6 stage6 slow fifo word6 0x1c8 [15:0] x r/ w stage6_sf_word7 stage6 slow fifo word7 0x1c9 [15:0] x r/ w stage6_sf_ambient stage6 slow fifo ambient value 0x1ca [15:0] x r/ w stage6_ff_avg stage6 fast fifo average value 0x1cb [15:0] x r/ w stage6_cdc_word0 stage0 cdc fifo word0 0x1cc [15:0] x r/ w stage6_cdc_word1 stage6 cdc fifo word1 0x1cd [15:0] x r/ w stage6_max_word0 stage6 maximum value fifo word0 0x1ce [15:0] x r/ w stage6_max_word1 stage6 maximum value fifo word1 0x1cf [15:0] x r/ w stage6_max_word2 stage6 maximum value fifo word2 0x1d0 [15:0] x r/ w stage6_max_word3 stage6 maximum value fifo word3 0x1d1 [15:0] x r/ w stage6_max_avg stage6 average maximum fifo value 0x1d2 [15:0] x r/ w stage6_high_threshold stage6 high threshold value 0x1d3 [15:0] x r/ w stage6_max_temp stage6 temporary maximum value 0x1d4 [15:0] x r/ w stage6_min_word0 stage6 minimum value fifo word0 0x1d5 [15:0] x r/ w stage6_min_word1 stage6 minimum value fifo word1 0x1d6 [15:0] x r/ w stage6_min_word2 stage6 minimum value fifo word2 0x1d7 [15:0] x r/ w stage6_min_word3 stage6 minimum value fifo word3 0x1d8 [15:0] x r/ w stage6_min_avg stage6 average minimum fifo value 0x1d9 [15:0] x r/ w stage6_low_threshold stage6 low threshold value 0x1da [15:0] x r/ w stage6_min_temp stage6 temporary minimum value 0x1db [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 55 of 56 table 50. stage7 results registers address data bit default value type mnemonic description 0x1dc [15:0] x r/ w stage7_conv_data stage7 cdc 16-bit conversion data (copy of data in cdc_result_s7 register) 0x1dd [15:0] x r/ w stage7_ff_word0 stage7 fast fifo word0 0x1de [15:0] x r/ w stage7_ff_word1 stage7 fast fifo word1 0x1df [15:0] x r/ w stage7_ff_word2 stage7 fast fifo word2 0x1e0 [15:0] x r/ w stage7_ff_word3 stage7 fast fifo word3 0x1e1 [15:0] x r/ w stage7_ff_word4 stage7 fast fifo word4 0x1e2 [15:0] x r/ w stage7_ff_word5 stage7 fast fifo word5 0x1e3 [15:0] x r/ w stage7_ff_word6 stage7 fast fifo word6 0x1e4 [15:0] x r/ w stage7_ff_word7 stage7 fast fifo word7 0x1e5 [15:0] x r/ w stage7_sf_word0 stage7 slow fifo word0 0x1e6 [15:0] x r/ w stage7_sf_word1 stage7 slow fifo word1 0x1e7 [15:0] x r/ w stage7_sf_word2 stage7 slow fifo word2 0x1e8 [15:0] x r/ w stage7_sf_word3 stage7 slow fifo word3 0x1e9 [15:0] x r/ w stage7_sf_word4 stage7 slow fifo word4 0x1ea [15:0] x r/ w stage7_sf_word5 stage7 slow fifo word5 0x1eb [15:0] x r/ w stage7_sf_word6 stage7 slow fifo word6 0x1ec [15:0] x r/ w stage7_sf_word7 stage7 slow fifo word7 0x1ed [15:0] x r/ w stage7_sf_ambient stage7 slow fifo ambient value 0x1ee [15:0] x r/ w stage7_ff_avg stage7 fast fifo average value 0x1ef [15:0] x r/ w stage7_cdc_word0 stage7 cdc fifo word0 0x1f0 [15:0] x r/ w stage7_cdc_word1 stage7 cdc fifo word1 0x1f1 [15:0] x r/ w stage7_max_word0 stage7 maximum value fifo word0 0x1f2 [15:0] x r/ w stage7_max_word1 stage7 maximum value fifo word1 0x1f3 [15:0] x r/ w stage7_max_word2 stage7 maximum value fifo word2 0x1f4 [15:0] x r/ w stage7_max_word3 stage7 maximum value fifo word3 0x1f5 [15:0] x r/ w stage7_max_avg stage7 average maximum fifo value 0x1f6 [15:0] x r/ w stage7_high_threshold stage7 high threshold value 0x1f7 [15:0] x r/ w stage7_max_temp stage7 temporary maximum value 0x1f8 [15:0] x r/ w stage7_min_word0 stage7 minimum value fifo word0 0x1f9 [15:0] x r/ w stage7_min_word1 stage7 minimum value fifo word1 0x1fa [15:0] x r/ w stage7_min_word2 stage7 minimum value fifo word2 0x1fb [15:0] x r/ w stage7_min_word3 stage7 minimum value fifo word3 0x1fc [15:0] x r/ w stage7_min_avg stage7 average minimum fifo value 0x1fd [15:0] x r/ w stage7_low_threshold stage7 low threshold value 0x1fe [15:0] x r/ w stage7_min_temp stage7 temporary minimum value 0x1ff [15:0] x unused set unused register bits to 0
AD7148 rev. 0 | page 56 of 56 outline dimensions compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bsc 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pad bottom view 122107-a figure 47. 16-lead frame chip scale package [lfcsp_vq] 4 mm 4 mm very thin quad (cp-16-13) dimensions shown in millimeters ordering guide model temperature range serial interface desc ription package description package option AD7148acpz-1reel 1 C40c to +85c i 2 c interface 16-lead lfcsp_vq cp-16-13 AD7148acpz-1500rl7 1 C40c to +85c i 2 c interface 16-lead lfcsp_vq cp-16-13 1 z = rohs compliant part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07155-0-12/07(0)

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